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參數(shù)資料
| 型號： | XRD98L63AIV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 4/41頁 |
| 文件大小： | 0K |
| 描述： | IC CCD DIGITIZER 12BIT 48TQFP |
| 標準包裝： | 250 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.6 V |
| 封裝/外殼： | 48-TQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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XRD98L63
12
Rev.1.01
Test Register
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Test
nofs2
*Reserved *Reserved *Reserved *Reserved
ADCin
NoCDS *Reserved *Reserved
default
0
1
0
The Test register is used to program various special modes of the chip.
* Reserved bits are for Exar Factory test only, do not modify these bits.
nofs2, analog scale offset control. 0=normal CCD signal conversion. 1=no scale offset at PGA.
ADCin, ADC direct analog input mode. 0=normal operation. 1=CCDin & REFin connect directly to ADC.
NoCDS, CDS By-Pass mode. 0=normal operation. 1=CCDin & REFin connect directly to PGA.
See the “Analog Front End” section (pg. 15) for information about nofs2 and NoCDS
See the “Analog to Digital Converter” section (pg. 18) for information about ADCin,
Polarity Register
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Polarity
PBLKpol
EOSpol
SBLKpol
SPIXpol
CALpol CLAMPpol FSYNCpol ADCpol
default
0
1
0
The Polarity register is used to program the polarity of the clock inputs. All the clock inputs (except the serial
interface SCLK) can be programmed to be active high or active low. 0=active low. 1=active high.
See the “Clock Polarity” section (pg. 22) for more information.
Clock Register
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Clock
ADCLKsel CLAMPopt CALonly
SPIXopt RSTreject DOclamp
default
0
1
The Clock register is used for programming various clocking options.
ADCLKsel, select internal or external ADC clock. 0=external ADCLK pin. 1=internal ADCLK.
CLAMPopt, DC restore biasing. 0=bias powered only when CLAMP is active. 1=bias always powered.
CALonly, line timing option. 0=CAL & CLAMP signals required. 1=only CAL signal required.
SPIXopt,
φ2 signal generation option. 0=φ2 is a function of SPIX. 1=φ2 is a function of SBLK & SPIX.
RSTreject, reset pulse rejection option. 0=
φ3 always ON. 1=φ3 switched to reject CCD reset pulse.
DOclamp, digital output clamp option. 0=disable clamp function. 1=PBLK forces digital outputs to OB[7:0]
See the “Analog Front End” section (pg. 15) for information about CLAMPopt.
See the “Pixel Rate Clocks, SBLK, SPIX, and ADCLK” section (pgs. 22-25) for information about ADCLKsel,
CAL only, SPIXopt and RSTreject.
See the “Other Chip Controls and Features” section (pg. 34) for information about DOclamp.
SBLK Delay, SPIX Delay and ADC Delay Registers
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SBLK Delay
SBdly[5]
SBdly[4]
SBdly[3]
SBdly[2]
SBdly[1]
SBdly[0]
default
0
SPIX Delay
SPdly[8]
SPdly[7]
SPdly[6]
SPdly[5]
SPdly[4]
SPdly[3]
SPdly[2]
SPdly[1]
SPdly[0]
default
0
ADC Delay
ADCdly[7] ADCdly[6] ADCdly[5] ADCdly[4] ADCdly[3] ADCdly[2] ADCdly[1] ADCdly[0]
default
0
SBdly[5:0], SPdly[8:0] and ADCdly[7:0] are used to program the internal aperture delay options. Each
register is divided into 2 or 3 delay parameters. For each delay parameter, minimum delay is all 0’s, and
maximum delay is all 1’s.
See the “Aperture Delays” section (pg. 26) for information about the Programmable Aperture Delays.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRD98L63AIVTR-F | 制造商:Exar Corporation 功能描述:AFE General Purpose 1ADC 12-Bit 3V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XRD98L63AIVTR-F |
| XRD98L63EVAL | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 Eval Board for XRD98L63AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L63ZEVAL | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 Eval Board (Solder) XRD98L63AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRDAN27 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Compensating for Zero Order Hold Effects |
| XRDAN28 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Frequency Response Effects of Overampling and Averaging on A/D Output Data |
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