Rev.1.01 TIMING: CLOCK BASICS There are 8 clock signals SBLK, SPIX, ADCLK, CLAMP, CAL, PBLK, EOS and Fsync. The pixel rate clocks a" />
參數(shù)資料
型號： XRD98L63AIV-F
廠商： Exar Corporation
文件頁數(shù)： 15/41頁
文件大?。?/td> 0K
描述： IC CCD DIGITIZER 12BIT 48TQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 12
通道數(shù)： 1
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.6 V
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
XRD98L63
22
Rev.1.01
TIMING: CLOCK BASICS
There are 8 clock signals SBLK, SPIX, ADCLK,
CLAMP, CAL, PBLK, EOS and Fsync.
The pixel rate clocks are SBLK, SPIX, and ADCLK.
SBLK controls sampling of the Black reference level
for each pixel. SPIX controls sampling of the Video
level for each pixel. ADCLK controls the ADC sampling
of the PGA output and ADC operation.
The line rate clocks are CLAMP, CAL, PBLK and EOS.
CLAMP controls the DC restore function for the exter-
nal AC coupling capacitors. CAL controls the Black
level calibration by defining the OB pixels at the start
or end of each line. In the One Shot mode (CAL only),
CLAMP is not used. PBLK is used to disconnect the
CDS from the CCDin & REFin pins during vertical shift
time. If the DOclamp bit in the Clock register is high,
PBLK will also force the digital output bus, DB[11:0], to
output the value in the Offset register, OB[7:0]. EOS
is used in the Multiple Gain mode to indicate if a line (or
field) is even or odd.
Clock Polarity
Each of the 8 clock pins has a separate polarity control
bit in the Polarity register. If the polarity bit for a clock
is low, then the clock is active low. If the polarity bit for
a clock is high, then the clock is active high. After reset
(by POR, Reset bit or XRESET pin), all clocks default
to active low; EOS defaults to active high.
Polarity
SBLK
SPIX
ADCLK
CAL
CLAMP
Aperture
Delays
Clock
Logic
AFE
ADC
Calibration
PBLK
EOS
Fsync
Figure 15. Clock Polarity & Aperture Delays
Figure 14. Pixel Timing Showing Pipeline Delay
Pipeline Delay
The digital outputs, DB[11:0] and OVER, are synchro-
nized to ADCLK. When ADCLKpol=0 (default), the
digital outputs change on the rising edge of ADCLK.
Figure 14 shows the pipeline delay (latency) from
sampling a pixel at the CDS input, until the correspond-
ing data is available at the digital output.
CCD
Signal
SBLK
SPIX
ADCLK
Black Level
Video
Level
DB[11:0]
sample
PGA1out
sample
black
sample
video
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bits 1&0
error
correction
Pixel N
Pixel N+1
Pixel N-1
Pixel N-2
Pixel N-3
Pixel N-4
Pixel N-5
Pixel N-6
Pixel N-7
7.5 Pixel Pipeline Delay
Pixel N-8
t
DL
sample
PGA2out
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參數(shù)描述
XRD98L63AIVTR-F 制造商:Exar Corporation 功能描述:AFE General Purpose 1ADC 12-Bit 3V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XRD98L63AIVTR-F
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