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參數(shù)資料
| 型號： | XR20V2172L64-0A-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 6/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR20V2170 64QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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XR20V2172
14
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.2
2.9
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks
(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same
manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4
word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR
interrupt is enabled by IER bit-0.
2.9.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 10. RECEIVER OPERATION IN NON-FIFO MODE
R eceive D ata Shift
R egister (R SR)
Receive
D ata Byte
and Errors
R H R Interrupt (ISR bit-2)
Receive Data
H olding R egister
(R H R)
R XFIFO 1
16X or 8X or 4X C lock
( D LD[5:4] )
R eceive Data Characters
D ata Bit
Validation
Error
Tags in
LSR bits
4:2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR20V2172L64-0B-EB | 功能描述:UART 接口集成電路 Supports V2172 64pin QFN, SPI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR-210 | 制造商:EXAR 制造商全稱:EXAR 功能描述:FSK MODULATOR / DEMODULATOR |
| XR-2100CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM |
| XR-2100CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM |
| XR-2103 | 制造商:EXAR 制造商全稱:EXAR 功能描述:FSK Modem Filter |
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