TABLE 6: TYPICAL DATA RATES WITH A 24 MH<" />
參數(shù)資料
型號(hào): XR20V2172L64-0A-EB
廠商: Exar Corporation
文件頁(yè)數(shù): 4/51頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR20V2170 64QFN
標(biāo)準(zhǔn)包裝: 1
系列: *
TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required
Output Data
Rate
DIVISOR FOR
16x Clock
(Decimal)
DIVISOR
OBTAINABLE IN
V2172
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DLD PROGRAM
VALUE (HEX)
DATA ERROR
RATE (%)
400
3750
E
A6
0
2400
625
2
71
0
4800
312.5
312 8/16
1
38
8
0
9600
156.25
156 4/16
0
9C
4
0
10000
150
0
96
0
19200
78.125
78 2/16
0
4E
2
0
25000
60
0
3C
0
28800
52.0833
52 1/16
0
34
1
0.04
38400
39.0625
39 1/16
0
27
1
0
50000
30
0
1E
0
57600
26.0417
26 1/16
0
1A
1
0.08
75000
20
0
14
0
100000
15
0
F
0
115200
13.0208
13
0
D
0
0.16
153600
9.7656
9 12/16
0
9
C
0.16
200000
7.5
7 8/16
0
7
8
0
225000
6.6667
6 11/16
0
6
B
0.31
230400
6.5104
6 8/16
0
6
8
0.16
250000
6
0
6
0
XR20V2172
12
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.2
2.8
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X
internal clock. A bit time is 16 (8 if 8X or 4 if 4X) clock periods (see DLD[5:4]). The transmitter sends the start-
bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The
status of the FIFO and TSR are reported in the Line Status Register (LSR[6:5]).
2.8.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
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