REV. 1.0.2 4.16 GPIO State Register (IOState) = Read/Wr" />
參數(shù)資料
型號(hào)： XR20V2172L64-0A-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 28/51頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR20V2170 64QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR20V2172
34
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.2
4.16
GPIO State Register (IOState) = Read/Write
This register reports the state of all GPIO pins during a read and writes to any GPIO that is an output.
Logic 0 = set output pin LOW
Logic 1 = set output pin HIGH
4.17
GPIO Interrupt Enable Register (IOIntEna) - Read/Write
This register enables the interrupt for the GPIO pins. The interrupts for GPIO[7:4] are only enabled if
IOControl[1] = 0. If IOControl[0] = 1 (GPIO pins are selected as modem IOs) , then IOIntEna[7:4] will have no
effect on GPIO[7:4].
Logic 0 = a change in the input pin will not generate an interrupt
Logic 1 = a change in the input will generate an interrupt
4.18
GPIO Control Register (IOControl) - Read/Write
IOControl bits 2-1 should be set to a logic 1 to behave like modem IOs that can be controlled and monitored via
the MCR and MSR registers. If not, by default, they are GPIOs controlled by IODir, IOState and IOIntEna.
IOControl[7:4]: Reserved
IOControl[3]: UART Software Reset
Writing a logic 1 to this bit will reset the device. Once the device is reset, this bit will automatically be set to a
logic 0.
IOControl[2]: GPIO[3:0] or Modem IO Select (CH B)
This bit controls whether GPIO[3:0] behave as GPIO pins or as modem IO pins (RIB#, CDB#, DTRB#, DSRB#)
Logic 0 = GPIO[3:0] behave as GPIO pins
Logic 1 = GPIO[3:0] behave as RIB#, CDB#, DTRB#, DSRB#. Note: DTRB# will also need to be set as an
output via IODir bit-1.
IOControl[1]: GPIO[7:4] or Modem IO Select (CH A)
This bit controls whether GPIO[7:4] behave as GPIO pins or as modem IO pins (RIA#, CDA#, DTRA#, DSRA#)
Logic 0 = GPIO[7:4] behave as GPIO pins
Logic 1 = GPIO[7:4] behave as RIA#, CDA#, DTRA#, DSRA#. Note: DTRA# will also need to be set as an
output via IODir bit-5.
IOControl[0]: IO Latch
This bit enable/disable GPIO inputs latching.
Logic 0 = GPIO input values are not latched. A change in any GPIO input generates an interrupt. A read of
the IOState register clears the interrupt. If the input goes back to its initial logic state before the input register
is read, then the interrupt is cleared.
Logic 1 = GPIO input values are latched. A change in the GPIO input generates an interrupt and the input
logic value is loaded in the bit of the corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial logic state before the interrupt register is
read, then the interrupt is not cleared and the corresponding bit of the IOState register keeps the logic value
that generated the interrupt.
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參數(shù)描述
XR20V2172L64-0B-EB 功能描述:UART 接口集成電路 Supports V2172 64pin QFN, SPI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR-210 制造商:EXAR 制造商全稱:EXAR 功能描述:FSK MODULATOR / DEMODULATOR
XR-2100CJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM
XR-2100CP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM
XR-2103 制造商:EXAR 制造商全稱:EXAR 功能描述:FSK Modem Filter
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