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參數(shù)資料
| 型號： | XR20V2172L64-0A-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 30/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR20V2170 64QFN |
| 標準包裝： | 1 |
| 系列： | * |
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XR20V2172
36
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.2
4.21
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
No TX and RX flow control (default and reset)
0
X
No transmit flow control
1
0
X
Transmit Xon1, Xoff1
0
1
X
Transmit Xon2, Xoff2
1
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
0
No receive flow control
X
1
0
Receiver compares Xon1, Xoff1
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 2 and 5-7,
TCR, TLR and DLD to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch
the new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 2
and 5-7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits
4-5, MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled (default).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR20V2172L64-0B-EB | 功能描述:UART 接口集成電路 Supports V2172 64pin QFN, SPI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR-210 | 制造商:EXAR 制造商全稱:EXAR 功能描述:FSK MODULATOR / DEMODULATOR |
| XR-2100CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM |
| XR-2100CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM |
| XR-2103 | 制造商:EXAR 制造商全稱:EXAR 功能描述:FSK Modem Filter |
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