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參數(shù)資料
| 型號： | XC3S50AN-5FTG256C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 93/123頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN-3AN 256FTBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-3AN |
| LAB/CLB數(shù)： | 176 |
| 邏輯元件/單元數(shù)： | 1584 |
| RAM 位總計(jì)： | 55296 |
| 輸入/輸出數(shù)： | 195 |
| 門數(shù)： | 50000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
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DS557 (v4.1) April 1, 2011
Product Specification
71
Copyright 2007–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Introduction
This section describes how the various pins on a Spartan-3AN FPGA connect within the supported component packages,
and provides device-specific thermal characteristics. For general information on the pin functions and the package
characteristics, see the Packaging section of UG331:
UG331: Spartan-3 Generation FPGA User Guide
Spartan-3AN FPGAs are available in Pb-free, RoHS packages, indicated by a “G” in the middle of the package code. Leaded
(Pb) packages are available for selected devices, with the same pinout and without the “G” in the ordering code (see Table 5,
page 7). The Pb-free package code can be selected in the software for the Pb packages since the pinouts are identical.
References to the Pb-free package code in this document apply also to the Pb package.
Pin Types
Most pins on a Spartan-3AN FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12 different
functional types of pins on Spartan-3AN FPGA packages, as outlined in Table 62. In the package footprint drawings that
follow, the individual pins are color-coded according to pin type as in the table.
123
Spartan-3AN FPGA Family:
Pinout Descriptions
DS557 (v4.1) April 1, 2011
Product Specification
Table 62: Types of Pins on Spartan-3AN FPGAs
Type with
Color Code
Description
Pin Name(s) in
Type(1)
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential
I/Os.
IO_#
IO_Lxxy_#
INPUT
Unrestricted, general-purpose input-only pin. This pin does not have an output structure,
differential termination resistor, or PCI clamp diode.
IP_#
IP_Lxxy_#
DUAL
Dual-purpose pin used in some configuration modes during the configuration process and then
usually available as a user I/O after configuration. If the pin is not used during configuration, this
pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation Configuration User Guide for
additional information on these signals.
M[2:0]
PUDC_B
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
DOUT
CSO_B
RDWR_B
INIT_B
A[25:0]
VS[2:0]
LDC[2:0]
HDC
VREF
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other VREF pins
in the same bank, provides a reference voltage input for certain I/O standards. If used for a
reference voltage within a bank, all VREF pins within the bank must be connected.
IP/VREF_#
IP_Lxx_#/VREF_#
IO/VREF_#
IO_Lxx_#/VREF_#
CLK
Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16 global
clock inputs that optionally clock the entire device. The exceptions are all devices in the TQG144
package and the XC3S50AN in the FTG256 package. The RHCLK inputs optionally clock the
right half of the device. The LHCLK inputs optionally clock the left half of the device. See the
Using Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for
additional information on these signals.
IO_Lxx_#/GCLK[15:0],
IO_Lxx_#/LHCLK[7:0],
IO_Lxx_#/RHCLK[7:0]
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