參數(shù)資料
型號(hào)： XC3S50AN-5FTG256C
廠(chǎng)商： Xilinx Inc
文件頁(yè)數(shù)： 69/123頁(yè)
文件大小： 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 176
邏輯元件/單元數(shù)： 1584
RAM 位總計(jì)： 55296
輸入/輸出數(shù)： 195
門(mén)數(shù)： 50000
電源電壓： 1.14 V ~ 1.26 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
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Spartan-3AN FPGA Family: Introduction and Ordering Information
DS557 (v4.1) April 1, 2011
Product Specification
5
Sector-based data protection and security features
Sector Protect: Write- and erase-protect a sector
(changeable)
Sector Lockdown: Sector data is unchangeable
(permanent)
128-byte Security Register
Separate from FPGA’s unique Device DNA
identifier
64-byte factory-programmed identifier unique to
the in-system Flash memory
64-byte one-time programmable,
user-programmable field
100,000 Program/Erase cycles
20-year data retention
Comprehensive programming support
In-system prototype programming via JTAG using
Xilinx Platform Cable USB and iMPACT software
Product programming support using BPM
Microsystems programmers with appropriate
programming adapter
Design examples demonstrating in-system
programming from a Spartan-3AN FPGA
application
I/O Capabilities
The Spartan-3AN FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 4
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination. Some of the user I/Os are unidirectional,
input-only pins as indicated in Table 4.
Spartan-3AN FPGAs support the following single-ended
standards:
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3.3V PCI at 33 MHz or 66 MHz
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
Spartan-3AN FPGAs support the following differential
standards:
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
Bus LVDS I/O at 2.5V
TMDS I/O at 3.3V
Differential HSTL and SSTL I/O
LVPECL inputs at 2.5V or 3.3V
Table 4: Available User I/Os and Differential (Diff) I/O Pairs
Package(1)
TQ144
TQG144
FT256
FTG256
FG400
FGG400
FG484
FGG484
FG676
FGG676
Body Size (mm)
20 x 20(2)
17 x17
21x 21
23x23
27 x 27
Device(3)
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
XC3S50AN
108(4)
(7)
50
(24)
144
(32)
64
(32)
–
XC3S200AN
–
195
(35)
90
(50)
–
XC3S400AN
–
195
(35)
90
(50)
311
(63)
142
(78)
–
XC3S700AN
–
372
(84)
165
(93)
–
XC3S1400AN
–
375
(87)
165
(93)
502
(94)
227
(131)
Notes:
1.
See Pb and Pb-Free Packaging, page 7 for details on Pb and Pb-free packaging options.
2.
The footprint for the TQ(G)144 (22 mm x 22 mm) package is larger than the package body.
3.
Each Spartan-3AN FPGA has a pin-compatible Spartan-3A FPGA equivalent, although Spartan-3A FPGAs do not have internal SPI flash
and offer more part/package combinations.
4.
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
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XC3S50AN-5TQG144C 功能描述:IC FPGA SPARTAN-3A 50K 144-TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Spartan®-3AN 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門(mén)數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱(chēng):220-1241
XC3S50J-4PQ208CES 制造商:Xilinx 功能描述:XLXXC3S50J-4PQ208CES IC LOGIC CELLS
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XC3S700A-4FG400C 功能描述:IC SPARTAN-3A FPGA 700K 400FBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Spartan®-3A 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門(mén)數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
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