參數(shù)資料
型號(hào)： XC3S50AN-5FTG256C
廠商： Xilinx Inc
文件頁數(shù)： 60/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 176
邏輯元件/單元數(shù)： 1584
RAM 位總計(jì)： 55296
輸入/輸出數(shù)： 195
門數(shù)： 50000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
41
Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions. Table 30 lists the conditions to use for each
standard.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of VL and a
High logic level of VH is applied to the Input under test.
Some standards also require the application of a bias
voltage to the VREF pins of a given bank to properly set the
input-switching threshold. The measurement point of the
Input signal (VM) is commonly located halfway between VL
and VH.
The Output test setup is shown in Figure 11. A termination
voltage VT is applied to the termination resistor RT, the other
end of which is connected to the Output. For each standard,
RT and VT generally take on the standard values
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
LVCMOS, LVTTL), then RT is set to 1M to indicate an
open connection, and VT is set to zero. The same
measurement point (VM) that was used at the Input is also
used at the Output.
X-Ref Target - Figure 11
Figure 11: Output Test Setup
FPGA Output
VT (VREF)
RT (RREF)
VM (VMEAS)
CL (CREF)
DS312-3_04_102406
Notes:
1.
The names shown in parentheses are
used in the IBIS file.
Table 30: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
Inputs
Outputs(2)
Inputs and
Outputs
VREF (V)
VL (V)
VH (V)
RT ()VT (V)
VM (V)
Single-Ended
LVTTL
–
0
3.3
1M
0
1.4
LVCMOS33
–
0
3.3
1M
0
1.65
LVCMOS25
–
0
2.5
1M
0
1.25
LVCMOS18
–
0
1.8
1M
0
0.9
LVCMOS15
–
0
1.5
1M
0
0.75
LVCMOS12
–
0
1.2
1M
0
0.6
PCI33_3
Rising
–Note 3
Note 3
25
0
0.94
Falling
25
3.3
2.03
PCI66_3
Rising
–Note 3
Note 3
25
0
0.94
Falling
25
3.3
2.03
HSTL_I
0.75
VREF – 0.5
VREF + 0.5
50
0.75
VREF
HSTL_III
0.9
VREF – 0.5
VREF + 0.5
50
1.5
VREF
HSTL_I_18
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
HSTL_II_18
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
HSTL_III_18
1.1
VREF – 0.5
VREF + 0.5
50
1.8
VREF
SSTL18_I
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
SSTL18_II
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
SSTL2_I
1.25
VREF – 0.75
VREF + 0.75
50
1.25
VREF
SSTL2_II
1.25
VREF – 0.75
VREF + 0.75
25
1.25
VREF
SSTL3_I
1.5
VREF – 0.75
VREF + 0.75
50
1.5
VREF
SSTL3_II
1.5
VREF – 0.75
VREF + 0.75
25
1.5
VREF
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