參數(shù)資料
型號： XC3S50AN-5FTG256C
廠商： Xilinx Inc
文件頁數(shù)： 90/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 176
邏輯元件/單元數(shù)： 1584
RAM 位總計： 55296
輸入/輸出數(shù)： 195
門數(shù)： 50000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
69
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
02/26/07
1.0
Initial release.
08/16/07
2.0
Updated for Production release of initial device (XC3S200AN). Timing specifications updated for v1.38
speed files. DC specifications updated with production values. Other changes throughout.
08/31/07
2.0.1
Updated for Production release of XC3S1400AN. Improved tPEP for XC3S700AN in Table 48.
09/12/07
2.0.2
Updated for Production release of XC3S700AN.
09/24/07
2.1
Updated for Production release of XC3S400AN. Updated Software Version Requirements to note that
Production speed files are available as of Service Pack 3. Removed PCIX IOSTANDARD due to limited
PCIX interface support. Added note that SPI_ACCESS (In-System Flash) is not currently supported in
simulation.
12/12/07
3.0
Updated to Production status with Production release of final family member, XC3S50AN. Noted that
SPI_ACCESS simulation is supported in ISE 10.1 software. Removed DNA_RETENTION limit of 10
years in Table 17 since number of Read cycles is the only unique limit. Updated Setup, Hold, and
Propagation Times for the IOB Input Path to show values by device in Table 23 and Table 25. Increased
SSO recommendation for SSTL18_II in Table 32. Updated Figure 17 and Table 59 to show BPI data
synchronous to CCLK rising edge. Updated links.
06/02/08
3.1
Improved VCCAUXT and VCCO2T POR minimum in Table 7 and updated VCCO POR levels in Figure 13.
Clarified power sequencing in Note 1 of Table 7, Table 8, and Figure 13. Added VIN to Recommended
Operating Conditions in Table 10 and added reference to XAPP459, “Eliminating I/O Coupling Effects
when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.” Reduced typical ICCINTQ and
ICCAUXQ quiescent current values by 12%-58% in Table 12. Noted latest speed file v1.39 in ISE 10.1
software in Table 19. Added reference to Sample Window in Table 24. Changed Internal SPI interface
max frequency to 50 MHz and updated other Internal SPI timing parameters to match names and
values from speed file in Table 47. Restored Units column to Table 49. Updated CCLK output maximum
period in Table 51 to match minimum frequency in Table 52. Added references to User Guides.
11/19/09
3.2
Updated selected I/O standard DC characteristics. Changed typical quiescent current temperature
from ambient to junction. Removed references to older software versions. Updated column 3 header
of Table 17 and Table 18. Added table note to Table 18. Added TIOPI and TIOPID propagation times in
Table 25. Updated TIOCKHZ and TIOCKON synchronous output enable/disable times in Table 28.
Removed VREF requirements for differential HSTL and differential SSTL in Table 30. Improved
DIFF_SSTL18_II SSO limits in Table 32. Updated table note 3 in Table 39. Removed references to old
software versions from Table 47 and Table 48. Added description of spread spectrum in Spread
Spectrum section. Updated BPI configuration waveforms in Figure 17. Updated TACC equation in
12/02/10
4.0
Added IIK to Table 6. Updated VIN in Table 10 and added a footnote to IL in Table 11 to note potential
leakage between pins of a differential pair. Added note 6 to Table 13. Corrected CLK High and Low
Time symbol in Table 46. Corrected symbols for TSUSPEND_GTS and TSUSPEND_GWE in Table 49.
Updated link to sign up for Alerts and updated Notice of Disclaimer.
04/01/11
4.1
In Table 31, added the equivalent pairs per bank for the XC3S50AN and XC3S400AN in the FT(G)256
package and the XC3S1400AN in the FG(G)484 package.
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