參數(shù)資料
型號(hào)： XC3S50AN-5FTG256C
廠商： Xilinx Inc
文件頁數(shù)： 85/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 176
邏輯元件/單元數(shù)： 1584
RAM 位總計(jì)： 55296
輸入/輸出數(shù)： 195
門數(shù)： 50000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
64
Slave Parallel Mode Timing
X-Ref Target - Figure 15
Figure 15: Waveforms for Slave Parallel Configuration
Table 56: Timing for the Slave Parallel Configuration Mode
Symbol
Description
All Speed Grades
Units
Min
Max
Setup Times
TSMDCC
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
7
–ns
TSMCSCC
Setup time on the CSI_B pin before the rising transition at the CCLK pin
7
–ns
Setup time on the RDWR_B pin before the rising transition at the CCLK pin
15
–ns
Hold Times
TSMCCD
The time from the rising transition at the CCLK pin to the point when data is last held at
the D0-D7 pins
1.0
–ns
TSMCCCS
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the CSO_B pin
0
–ns
TSMWCC
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the RDWR_B pin
0
–ns
Clock Timing
TCCH
The High pulse width at the CCLK input pin
5
–ns
TCCL
The Low pulse width at the CCLK input pin
5
–ns
FCCPAR
Frequency of the clock signal
at the CCLK input pin
No bitstream compression
0
80
MHz
With bitstream compression
0
80
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10.
2.
Some Xilinx documents refer to Parallel modes as SelectMAP modes.
DS529-3_02_051607
Byte 0
Byte 1
Byte n
Byte n+1
T
SMWCC
1/F
CCPAR
T
SMCCCS
T
SCCH
T
SMCCW
T
SMCCD
T
SMCSCC
T
SMDCC
PROG_B
(Input)
(Open-Drain)
INIT_B
(Input)
CSI_B
RDWR_B
(Input)
CCLK
(Inputs)
D0 - D7
T
MCCH
T
SCCL
T
MCCL
Notes:
1.
It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0–D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0–D7 bus.
2.
To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332, Chapter 7, section “Non-Continuous SelectMAP Data
Loading” for more details.
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