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參數(shù)資料
| 型號： | X40239 |
| 廠商： | Intersil Corporation |
| 英文描述： | Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP |
| 中文描述： | 三電壓監(jiān)測器，葡萄牙，2千比特EEPROM存儲(chǔ)器，以及單/雙副處長 |
| 文件頁數(shù)： | 4/36頁 |
| 文件大小： | 541K |
| 代理商： | X40239 |
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4
FN8115.0
April 11, 2005
X40233 PIN ASSIGNMENT
SOIC
1
2
Name
NC
NC
Function
No Connect
No Connect
V3MON Voltage Monitor Input.
V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than
the V
TRIP3
threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V
SS
when
not used.
V3MON RESET Output.
This open drain output makes a transition to a HIGH level when V3MON is greater than V
TRIP3
and goes
LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires
the use of an external “pull-up” resistor.
Manual Reset.
MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET
pin (V
CC
RESET Output pin). RESET will remain HIGH for time t
PURST
after MR has returned to it’s
normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The
MR pin requires the use of an external “pull-down” resistor.
Write Protect Control Pin.
WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and
the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile
or nonvolatile) operations can be performed in the device (including the wiper position of any of the
integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor,
thus if left floating the write protection feature is disabled.
Serial Clock.
This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data.
SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA
pin input buffer is always active (not gated). This pin requires an external pull up resistor.
Ground.
3
V3MON
4
V3FAIL
5
MR
6
WP
7
SCL
8
SDA
9
VSS
R
W1
R
H1
NC
10
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP.
11
Connection to end of resistor array for (the 100 Tap) DCP.
12
No Connect
V2MON Voltage Monitor Input.
V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than
the V
TRIP2
threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V
SS
when
not used.
V2MON RESET Output.
This open drain output makes a transition to a HIGH level when V2MON is greater than V
TRIP2
, and goes
LOW when V2MON is less than V
TRIP2
. There is no power-up reset delay circuitry on this pin. The
V2FAIL pin requires the use of an external “pull-up” resistor.
V
CC
RESET Output.
This is an active HIGH, open drain output which becomes active whenever V
CC
falls below V
TRIP1
.
RESET becomes active on power-up and remains active for a time t
PURST
after the power supply
stabilizes (t
PURST
can be changed by varying the PUP0 and PUP1 bits of the internal control register).
The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active
(HIGH) using the manual reset (MR) input pin.
13
V2MON
14
V2FAIL
15
RESET
16
V
CC
Supply Voltage.
X40231, X40233, X40235, X40237, X40239
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