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參數(shù)資料
| 型號： | X40239 |
| 廠商： | Intersil Corporation |
| 英文描述： | Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP |
| 中文描述： | 三電壓監(jiān)測器，葡萄牙，2千比特EEPROM存儲器，以及單/雙副處長 |
| 文件頁數(shù)： | 19/36頁 |
| 文件大小： | 541K |
| 代理商： | X40239 |
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19
FN8115.0
April 11, 2005
When the Block Lock bits of the CR register are set to
something other than BL1 = 0 and BL0 = 0, then the
“wiper position” of the DCPs cannot be changed - i.e.
DCP write operations cannot be conducted:
The factory default setting for these bits are BL1 = 0,
BL0 = 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of
the X4023x is active (HIGH), then all nonvolatile write
operations to both the EEPROM memory and DCPs
are inhibited, irrespective of the Block Lock bit settings
(See "WP: Write Protection Pin").
PUP1, PUP0: Power-on Reset bits – (Nonvolatile)
Applying voltage to V
CC
activates the Power-on Reset
circuit which holds RESET output HIGH, until the sup-
ply voltage stabilizes above the V
TRIP1
threshold for a
period of time, t
PURST
(See Figure 30).
The Power-on Reset bits, PUP1 and PUP0 of the CR
register determine the t
PURST
delay time of the Power-
on Reset circuitry (See "VOLTAGE MONITORING
FUNCTIONS"). These bits of the CR register are non-
volatile, and therefore power-up to the last written
state.
The nominal Power-on Reset delay time can be
selected from the following table, by writing the appro-
priate bits to the CR register:
The default for these bits are PUP1 = 0, PUP0 = 1.
V2FS, V3FS: Voltage Monitor Status Bits (Volatile)
Bits V2FS and V3FS of the CR register are latched,
volatile flag bits which indicate the status of the Volt-
age Monitor reset output pins V2FAIL and V3FAIL.
At power-up the VxFS (x=2,3) bits default to the value
“0”. These bits can be set to a “1” by writing the appro-
priate value to the CR register. To provide consistency
between the VxFAIL and V
xFS
however, the status of
the V
xFS
bits can only be set to a “1” when the corre-
sponding VxFAIL output is HIGH.
Once the VxFS bits have been set to “1”, they will be
reset to “0” if:
—The device is powered down, then back up,
—The corresponding V
xFAIL
output becomes LOW.
CR Register Write Operation
The CR register is accessed using the Slave Address
set to 1010010 (Refer to Figure 4). Following the
Slave Address Byte, access to the CR register
requires an Address Byte which must be set to FFh.
Only one data byte is allowed to be written for each
CR register Write operation. The user must issue a
STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the BP1, BP0, PUP1
and PUP0 bits. The X4023x will not ACKNOWLEDGE
any data bytes written after the first byte is entered
(Refer to Figure 18).
BL1
0
0
1
1
BL0
0
1
0
1
DCP Write Operation Permissible
YES (Default)
NO
NO
NO
PUP1
0
0
1
1
PUP0
0
1
0
1
Power-on Reset delay (t
PURESET
)
50ms
100ms (Default)
200ms
300ms
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
C
K
1
1
1
1
1
1
1
1
A
C
K
SCL
SDA
S
T
O
P
A
C
K
CS7 CS6CS5 CS4 CS3 CS2CS1 CS0
SLAVE ADDRESS BYTE
ADDRESS BYTE
CR REGISTER DATA IN
Figure 18. CR Register Write Command Sequence
X40231, X40233, X40235, X40237, X40239
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