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參數(shù)資料
| 型號(hào)： | X40239 |
| 廠商： | Intersil Corporation |
| 英文描述： | Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP |
| 中文描述： | 三電壓監(jiān)測器，葡萄牙，2千比特EEPROM存儲(chǔ)器，以及單/雙副處長 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大小： | 541K |
| 代理商： | X40239 |
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11
FN8115.0
April 11, 2005
At both ends of each array and between each resistor
segment there is a CMOS switch connected between
the resistor array and the wiper (R
w
x
) output. Within
each individual array, only one switch may be turned
on at any one time. These switches are controlled by
the Wiper Counter Register (WCR) (See Figure 6).
The WCR is a volatile register.
On power-up of the X4023x, wiper position data is au-
tomatically loaded into the WCR from its associated
Non Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap posi-
tion to another.
Hot Pluggability
Figure 7 shows a typical waveform that the X4023x
might experience in a Hot Pluggable situation. On
power-up, V
CC
applied to the X4023x may exhibit
some amount of ringing, before it settles to the
required value.
The device is designed such that the wiper terminal
(R
Wx
) is recalled to the correct position (as per the last
stored in the DCP NVM), when the voltage applied to
V
CC
exceeds V
TRIP1
for a time exceeding t
PURST
(the
Power-on Reset time, set in the CR Register - See
“CONTROL AND STATUS REGISTER” on page 18.).
Therefore, if
t
trans
is defined as the time taken for V
CC
to settle above V
TRIP1
(Figure 7): then the desired
wiper terminal position is recalled by (a maximum)
time:
t
trans
+
t
PURST
. It should be noted that
t
trans
is
determined by system hot plug conditions.
DCP Operations
In total there are three operations that can be per-
formed on any internal DCP structure:
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
ACK
returned
Issue Slave Address
Byte (Read or Write)
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
High Voltage Cycle
complete. Continue
command sequence
Issue STOP
NO
Continue normal
Read or Write
command sequence
PROCEED
YES
Figure 5.
Acknowledge Polling Sequence
DECODER
RESISTOR
ARRAY
R
Hx
FET
SWITCHES
R
Wx
0
1
2
N
WIPER
COUNTER
REGISTER
(WCR)
NON
MEMORY
(NVM)
VOLATILE
“WIPER”
Figure 6.
DCP Internal Structure
DCP
Initial Values Before Recall
V
H
(TAP = 63)
V
L
(TAP = 0)
V
H
(TAP = 255)
R
0
(64 TAP)
R
1
(100 TAP)
R
2
(256 TAP)
X40231, X40233, X40235, X40237, X40239
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