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參數(shù)資料
| 型號： | W947D6HBHX5E |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 5 ns, PBGA60 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60 |
| 文件頁數(shù)： | 19/60頁 |
| 文件大?。?/td> | 1160K |
| 代理商： | W947D6HBHX5E |
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W947D6HB / W947D2HB
128Mb Mobile LPDDR
Publication Release Date:Jun,17, 2011
- 26 -
Revision A01-003
7.3.2 Mode Register Set Command Timing
CK
Command
MRS
: Don't Care
NOTE:Code=Mode Register / Extended Mode Register selection
(BA0,BA1)and op-code (A0-An)
Code
Valid
NOP
tMRD
Address
7.4. Active
Before any READ or WRITE commands can be issued to a bank in the LPDDR SDRAM, a row in that bank must be
opened. This is accomplished by the ACTIVE command: BA0 and BA1 select the bank, and the address inputs
select the row to be activated. More than one bank can be active at any time.
Once a row is open, a READ or WRITE command could be issued to that row, subject to the tRCD specification.
A subsequent ACTIVE command to another row in the same bank can only be issued after the previous row has
been closed. The minimum time interval between two successive ACTIVE commands on the same bank is defined
by tRC.
7.4.1 Active Command
= Don't Care
(High)
CK
CKE
CS
RAS
CAS
WE
A0-An
BA0,BA1
RA
BA
BA=BANK Address, RA=Row
Address
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WS57C256F-70LMB | 32K X 8 UVPROM, 70 ns, CQCC32 |
| WMS128K8C-120FEIEA | 128K X 8 STANDARD SRAM, 120 ns, CDFP32 |
| WMS128K8L-100FEIE | 128K X 8 STANDARD SRAM, 100 ns, CDFP32 |
| WMS128K8L-120FECEA | 128K X 8 STANDARD SRAM, 120 ns, CDFP32 |
| WMS128K8L-120DRIEA | 128K X 8 STANDARD SRAM, 120 ns, CDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W947D6HBHX5I | 制造商:WINBOND 制造商全稱:Winbond 功能描述:128Mb Mobile LPDDR |
| W947D6HBHX5I TR | 制造商:Winbond Electronics Corp 功能描述: |
| W947D6HBHX6E | 制造商:Winbond Electronics Corp 功能描述:IC LPDDR SDRAM 128MBIT 60VFBGA |
| W947D6HBHX6G | 制造商:WINBOND 制造商全稱:Winbond 功能描述:128Mb Mobile LPDDR |
| W948D2FB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:256Mb Mobile LPDDR |
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