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參數(shù)資料
| 型號： | W25Q80BVSSIG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.208 INCH, GREEN, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 3/75頁 |
| 文件大?。?/td> | 1055K |
| 代理商： | W25Q80BVSSIG |
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W25Q80BV
condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data
Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip
Select (/CS) signal should be kept active low for the full duration of the /HOLD operation to avoid resetting
the internal logic state of the device.
Publication Release Date: October 06, 2010
- 11 -
Revision D
8.2
WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25Q80BV
provides several means to protect the data from inadvertent writes.
8.2.1
Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Status Register
Write Protection using Power-down instruction
Lock Down write protection until next power-up
One Time Program (OTP) write protection
*
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q80BV will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 38). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS can be used to
accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-
disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits.
These settings allow a portion as small as 4KB sector or the entire memory array to be configured as
read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be
enabled or disabled under hardware control. See Status Register section for further information.
Additionally, the Power-down instruction offers an extra level of write protection as all instructions are
ignored except for the Release Power-down instruction.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q80BVSSIG TR | 制造商:Winbond Electronics Corp 功能描述:SPIFLASH, 8M-BIT, 4KB UNIFORM 制造商:Winbond Electronics Corp 功能描述:IC FLASH 8MBIT 104MHZ 8SOIC |
| W25Q80BVSSIG/REELS | 制造商:Winbond Electronics Corp 功能描述: |
| W25Q80BVSSIG-T | 制造商:Winbond Electronics 功能描述:8MB SPI FLASH |
| W25Q80BVSSIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q80BVZPAG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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