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參數(shù)資料
| 型號： | W25Q64CVZPAP |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 64M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 6 X 5 MM, GREEN, WSON-8 |
| 文件頁數(shù)： | 31/79頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | W25Q64CVZPAP |
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W25Q64CV
Publication Release Date: April 01, 2011
- 37 -
Revision C
7.2.17 Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are
not required, which further reduces the instruction overhead allowing even faster random access for code
execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word
Read Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 16a. The
upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through
the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the E3h instruction code, as shown in Figure 16b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before
issuing normal instructions (See 7.2.20 for detail descriptions).
M7-0
/CS
CLK
Mode 0
Mode 3
0
1
IO
0
IO
1
IO
2
IO
2
3
4
5
20
16
12
8
21
17
22
18
23
19
13
9
14
10
15
11
A23-16
6
7
8
9
4
0
5
1
6
2
7
3
A15-8
A7-0
4
Byte 1
Byte 2
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
10
11
12
13
14
4
5
6
7
IOs switch from
Input to Output
Byte 3
15
16
17
18
19
20
21
Instruction (E3h)
4
0
5
1
6
2
7
3
Byte 4
Figure 16a. Octal Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4
≠ 10)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WMS128K8C-25CQE | 128K X 8 STANDARD SRAM, 25 ns, CDIP32 |
| WMF512K8X-150DEC5 | 512K X 8 FLASH 5V PROM, 150 ns, CDSO32 |
| WME128K8X-200DEC | 128K X 8 EEPROM 5V, 200 ns, CDSO32 |
| WMF512K8X-70FEM5 | 512K X 8 FLASH 5V PROM, 70 ns, CDFP32 |
| WMF512K8X-90CM5 | 512K X 8 FLASH 5V PROM, 90 ns, CDIP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q64CVZPIG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVZPIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64DW | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1.8V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI |
| W25Q64DWSFIG | 功能描述:IC FLASH SPI 64MBIT 16SOIC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:SpiFlash® 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
| W25Q64DWSFIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1.8V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI |
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