參數(shù)資料
型號(hào): W25B20-VSNIG
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 2M X 1 FLASH 2.7V PROM, PDSO8
封裝: 0.150 INCH, GREEN, PLASTIC, SOIC-8
文件頁數(shù): 2/36頁
文件大?。?/td> 1424K
代理商: W25B20-VSNIG
W25B40/W25B40A
- 10 -
7.2.2
Write Protection using Power-down instruction.
Upon power-up or at power-down the W25B40 / W25B40A will maintain a reset condition while VCC
is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 18). While
reset, all operations are disabled and no instructions are recognized. During power-up and after the
VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time
delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Chip Erase and the Write
Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at
power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS
can be used to accomplish this.
After power-up the device in automatically placed in a write-disabled state with the Status Register
Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page
Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After
completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically
cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP) and Block Protect (BP2, BP1, and BP0) bits. These Status Register
bits allow a portion or all of the memory to be configured as read only. Used in conjunction with the
Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware
control. See Status Register for further information.
Additionally, the Power-down instruction offers an extra level of write protection as all instructions are
ignored except for the Release Power-down instruction.
8. CONTROL AND STATUS REGISTERS
The Read Status Register instruction can be used to provide status on the availability of the Flash
memory array, if the device is write enabled or disabled, and the state of write protection. The Write
Status Register instruction can be used to configure the devices write protection features. See Figure
3.
8.1 STATUS REGISTER
8.1.1
BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing
a Page Program, Sector Erase, Chip Erase or Write Status Register instruction. During this time the
device will ignore further instructions except for the Read Status Register instruction (see tW, tPP, tSE
and tCE in AC Characteristics). When the program, erase or write status register instruction has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further
instructions.
8.1.2
Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing
a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A
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