參數(shù)資料
型號(hào): V58C365164S5
廠商: MOSEL-VITELIC
元件分類: DRAM
英文描述: 4M X 16 DDR DRAM, 0.1 ns, PDSO66
封裝: 0.400 INCH, PLASTIC, TSOP2-66
文件頁(yè)數(shù): 9/44頁(yè)
文件大?。?/td> 507K
代理商: V58C365164S5
17
V58C365164S Rev. 1.5 November 2001
MOSEL VITELIC
V58C365164S
Burst Write Timing
Once the burst of write data is concluded and given that no subsequent burst write operations are initiated,
the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe “write postamble”. This transition happens nominally one-half clock period after the last data of the
burst cycle is latched into the device.
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
WRITE
NOP
D0
D1
D2
D3
CK, CK
Command
DQS(nom)
DQ(nom)
tWPRES
tWPREH
tDQSS
tWPST
tQDQSH
D0
D1
D2
D3
DQS(min)
DQ(min)
tDQSS(min)
D0
D1
D2
D3
DQS(max)
DQ(max)
tWPRES(min)
tDQSS(max)
tQDQSS
tQDQSH
tWPREH(min)
tWPREH(max)
tWPRES(max)
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