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參數(shù)資料
| 型號： | V58C365164S5 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 DDR DRAM, 0.1 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 8/44頁 |
| 文件大?。?/td> | 507K |
| 代理商： | V58C365164S5 |
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16
V58C365164S Rev. 1.5 November 2001
MOSEL VITELIC
V58C365164S
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by a precharge of the same bank. The Precharge command to
Output Disable latency is equivalent to the CAS latency.
Read Interrupted by a Precharge Timing
Burst Write Operation
The Burst Write command is issued by having CS,CAS,and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. The memory controller is re-
quired to provide an input data strobe (DQS) to the DDR SDRAM to strobe or latch the input data (DQ) and
data mask (DM) into the device. During Write cycles, the data strobe applied to the DDR SDRAM is required
to be nominally centered within the data (DQ) and data mask (DM) valid windows. The data strobe must be
driven high nominally one clock after the write command has been registered. Timing parameters tDQSS(min)
and tDQSS(max) define the allowable window when the data strobe must be driven high.
Input data for the first Burst Write cycle must be applied one clock cycle after the Write command is regis-
tered into the device (WL=1). The input data valid window is nominally centered around the midpoint of the
data strobe signal. The data window is defined by DQ to DQS setup time (tQDQSS) and DQ to DQS hold time
(tQDQSH). All data inputs must be supplied on each rising and falling edge of the data strobe until the burst
length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored.
Write Preamble and Postamble Operation
Prior to a burst of write data and given that the controller is not currently in burst write mode, the data strobe
signal (DQS), must transition from Hi-Z to a valid logic low. This is referred to as the data strobe “write preamble”.
This transition from Hi-Z to logic low nominally happens on the falling edge of the clock after the write com-
mand has been registered by the device. The preamble is explicitly defined by a setup time (t
WPRES(min)) and
hold time (t
WPREH(min)) referenced to the first falling edge of CK after the write command.
T0
T1
T2
T3
T4
T5
T6
T7
T8
D0
D1
D2
D3
NOP
Read
NOP
PreA
NOP
BA
NOP
CK, CK
Command
DQS
DQ
tRAS(min)
tRP(min)
BA
NOP
T9
D0
D1
D2
D3
DQS
DQ
D0
D1
D2
D3
DQS
DQ
CAS Latency=2
CAS Latency=2.5
CAS Latency=3
(CAS Latency = 2, 2.5, 3; Burst Length = 8)
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