參數(shù)資料
型號(hào)： V58C365164S5
廠商： MOSEL-VITELIC
元件分類(lèi)： DRAM
英文描述： 4M X 16 DDR DRAM, 0.1 ns, PDSO66
封裝： 0.400 INCH, PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 24/44頁(yè)
文件大?。?/td> 507K
代理商： V58C365164S5
30
V58C365164S Rev. 1.5 November 2001
MOSEL VITELIC
V58C365164S
Clock Enable (CKE) Truth Table
Abbreviations:
RA = Row Address
BS = Bank Select Address
CA = Column Address
AP = Auto Precharge
Notes for SDRAM function truth table:
1. Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preceding clock cycle.
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in Idle state. The precharge bank(s) indicated by BS and AP.
5. Illegal if any bank is not Idle.
6. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any
command other than EXIT.
7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
8. Must be legal command as defined in the SDRAM function truth table.
STATE(n)
CKE
n-1
CKE
nCS
RAS
CAS
WE
Addr
ACTION
Self-Refresh6
H
L
X
H
L
X
H
L
X
H
L
X
H
L
X
H
L
X
INVALID
EXIT Self-Refresh, Idle after tRC
ILLEGAL
NOP (Maintain Self-Refresh)
Power-Down
H
L
X
H
L
X
H
L
X
H
L
X
H
L
X
H
L
X
INVALID
EXIT Power-Down, > Idle.
ILLEGAL
NOP (Maintain Low-Power Mode)
All. Banks
Idle
7
H
L
H
L
X
H
L
X
H
L
X
H
L
H
L
X
H
L
X
H
L
X
Refer to the function truth table
Enter Power- Down
ILLEGAL
Enter Self-Refresh
ILLEGAL
NOP
Any State
other than
listed above
H
L
H
L
H
L
X
Refer to the function truth table
Begin Clock Suspend next cycle8
Exit Clock Suspend next cycle8.
Maintain Clock Suspend.
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