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參數(shù)資料
| 型號： | V58C365164S5 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 DDR DRAM, 0.1 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 17/44頁 |
| 文件大?。?/td> | 507K |
| 代理商： | V58C365164S5 |
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V58C365164S Rev. 1.5 November 2001
MOSEL VITELIC
V58C365164S
SSTL_2 Input AC/DC Logic Levels
Note: 1. The relationship of the VDDQ of the driving device and the VREF of the receiving device is what determines noise margins.
However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the case where
a device is implemented such that supports SSTL_2 inputs but has no SSTL_2 outputs (e.g., a translator), and therefore no
VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0V (High corner VDDQ+300mV.)
SSTL_2 AC Test Conditions
Notes: 1. Input waveform timing is referenced to the input signal crossing the VREF level applied to the device.
2. Compliant devices must still meet the VIH (AC) and VIL (AC) specifications under actual use conditions.
3. The 1 V/ns input signal minimum slew rate is to be maintained in the VIL max (AC) to VIL min (AC) range of the input
signal swing.
SSTL_2 Output Buffers
The input voltage provided to the receiver depends on three parameters:
s VDDQ and current drive capabilities of the output buffer
s Termination voltage
s Termination resistance
s V
DDQ VDD
Class II SSTL_2 Output Buffer (Driver)
Symbol
Parameter
Min
Max
Units
Notes
VIH (DC)
DC Input Logic High
VREF+0.18
VDDQ+0.3
V
1
VIH (AC)
AC Input Logic High
VREF+0.35
—
V
VIL (DC)
DC Input Logic Low
–0.30
VREF–0.18
V
VIL (AC)
AC Input Logic Low
—
VREF–0.35
V
Symbol
Parameter
Value
Units
Notes
VREF
Input Reference Voltage
0.5*VDDQ
V1
VSWING (max)
Input Signal Maximum Peak to Peak Swing
1.5
V
1, 2
SLEW
Input Signal Minimum Slew Rate
1.0
V/ns
3
VREF
VIN
VTT = 0.5 *VDDQ
CLOAD = 30pF
VDDQ
VSSQ
VOUT
Receiver
RT=50
Output
Buffer
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