參數(shù)資料
型號(hào): V58C365164S5
廠商: MOSEL-VITELIC
元件分類: DRAM
英文描述: 4M X 16 DDR DRAM, 0.1 ns, PDSO66
封裝: 0.400 INCH, PLASTIC, TSOP2-66
文件頁(yè)數(shù): 44/44頁(yè)
文件大?。?/td> 507K
代理商: V58C365164S5
9
V58C365164S Rev. 1.5 November 2001
MOSEL VITELIC
V58C365164S
Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK)
During Read Cycles
The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a mem-
ory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to
the output data. The minimum data output valid time (tDV) and minimum data strobe valid time (tDQSV) are de-
rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to
DLL jitter and power supply noise.
(CAS Latency = 2.5; Burst Length = 4)
T0
T1
T2
T3
T4
NOP
D0
CK, CK
Command
DQS
DQ
D2
tDQSCK(max)
tDQSCK(min)
D1
tAC(min)
tAC(max)
D3
READ
NOP
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