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參數(shù)資料
| 型號(hào)： | V58C365164S5 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 DDR DRAM, 0.1 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-66 |
| 文件頁(yè)數(shù)： | 7/44頁(yè) |
| 文件大小： | 507K |
| 代理商： | V58C365164S5 |
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15
V58C365164S Rev. 1.5 November 2001
MOSEL VITELIC
V58C365164S
Burst Stop Command
The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS
high with CS and WE low at the rising edge of the clock. When the Burst Stop command is issued during a
burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay
(L
BST) equal to the CAS latency programmed into the device. If the Burst Stop command is issued during a
burst Write cycle, the command will be treated as a NOP command.
Read Terminated by Burst Stop Command Timing
(CAS Latency = 2, 2.5, 3; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
BST
NOP
Read
D0
D1
CK, CK
Command
DQS
DQ
D0
D1
DQS
DQ
D0
D1
DQS
DQ
CAS Latency = 2
CAS Latency = 2.5
CAS Latency = 3
LBST
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