參數(shù)資料
型號: V58C2256324SAH-36
廠商: PROMOS TECHNOLOGIES INC
元件分類: DRAM
英文描述: 8M X 32 DDR DRAM, 0.55 ns, PBGA144
封裝: ROHS COMPLIANT, BGA-144
文件頁數(shù): 6/37頁
文件大?。?/td> 370K
代理商: V58C2256324SAH-36
14
V58C2256324SA Rev. 1.4 August 2007
ProMOS TECHNOLOGIES
V58C2256324SA
Auto Refresh
The auto refresh function is initiated by issuing an Auto Refresh command at the rising edge of the clock. All banks must be precharged
and idle before the Auto Refresh command is applied. No control of the external address pins is required once this cycle has started. All
necessary addresses are generated in the device itself. When the refresh cycle has completed, all banks will be in the idle state. A delay
between the Auto Refresh command and the next Activate Command or subsequent Auto Refresh Command must be greater than or
equal to the t RFC(min).
Autorefresh timing
Power Down Mode
The Power Down Mode is entered when CKE is set low and exited when CKE is set high. The CKE signal is sampled at the rising edge
of the clock. Once the Power Down Mode is initiated, all of the receiver circuits except CLK, CKE and DLL circuits are gated off to reduce
power consumption. All banks can be set to idle state or stay activate during Power Down Mode, but burst activity may not be performed.
After exiting from Power Down Mode, at least one clock cycle of command delay must be inserted before starting a new command.
During Power Down Mode, refresh operations cannot be performed; therefore, the device cannot remain in Power Down Mode longer
than the refresh period (t REF) of the device.
Power Down Mode timing
Clk
Command
NOP
t
RFC
CKE
PRE-
CHARGE
AUTO
REFRESH
Command
t
RP
NOP
Command is
AUTOREFRESH
or ACT
Clk
Command
PRE
t
PDEX
CKE
NOP
Any
Command
Power Down
Mode entry
NOP
DESEL
Power Down
Mode exit
NOP
DESEL
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