參數(shù)資料
型號: V58C2256324SAH-36
廠商: PROMOS TECHNOLOGIES INC
元件分類: DRAM
英文描述: 8M X 32 DDR DRAM, 0.55 ns, PBGA144
封裝: ROHS COMPLIANT, BGA-144
文件頁數(shù): 10/37頁
文件大?。?/td> 370K
代理商: V58C2256324SAH-36
18
V58C2256324SA Rev. 1.4 August 2007
ProMOS TECHNOLOGIES
V58C2256324SA
Burst Stop Command (BST)
A Burst Stop is initiated by issuing a BURST STOP command at the rising edge of the clock. The Burst Stop Command has the fewest
restrictions, making it the easiest method to terminate a burst operation before it has been completed. When the Burst Stop Command
is issued during a burst read cycle, read data and DQSx go to a high impedance state after a delay which is equal to the CAS Latency
set in the Mode Register. The Burst Stop latency is equal to the CAS latency CL.The Burst Stop command is not supported during a
write burst operation. Burst Stop is also illegal during Read with Auto-Precharge.
Burst Stop for Read
CLK
READ
Command
BST
NOP
Burst length = 2
DQSx
DQx
D-out
0
D-out
1
CAS latency = 3
CL = 3
Burst Stop Latency = 3
DQSx
DQx
CAS latency = 4
D-out
0
D-out
1
Burst Stop Latency = 4
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