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參數(shù)資料
| 型號(hào)： | V58C2256324SAH-36 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.55 ns, PBGA144 |
| 封裝： | ROHS COMPLIANT, BGA-144 |
| 文件頁數(shù)： | 3/37頁 |
| 文件大?。?/td> | 370K |
| 代理商： | V58C2256324SAH-36 |
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V58C2256324SA Rev. 1.4 August 2007
ProMOS TECHNOLOGIES
V58C2256324SA
Bank Activation Command (ACT)
The Bank Activation command is initiated by issuing an ACT command at the rising edge of the clock. The DDR SDRAM has four
independent banks which are selected by the two Bank select Addresses (BA0, BA1). The Bank Activation command must be applied
before any Read or Write operation can be executed. The delay from the Bank Activation command to the first read or write command
must meet or exceed the minimum of RAS to CAS delay time (tRCDRD min. for read commands and tRCDWR min. for write commands).
Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The
minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank activation
delay time (tRRD min).
Activate to Read or Write Command Timing (one bank)
Activate Bank A to Activate Bank B Timing
Clk
Command
t
RCDWR for write
Bank A
ACT
t
RCDRD for read
t
RC
Addresses
Row Add.
READ
WRITE
or
Bank A
Col. Add.
Bank A
PRE
NOP
ACT
Bank A
Row Add.
Clk
Command
Bank A
ACT
t
RRD
Addresses
Row Add.
NOP
ACT
Bank B
Row Add.
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