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參數(shù)資料
| 型號(hào)： | V58C2256324SAH-36 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.55 ns, PBGA144 |
| 封裝： | ROHS COMPLIANT, BGA-144 |
| 文件頁數(shù)： | 36/37頁 |
| 文件大小： | 370K |
| 代理商： | V58C2256324SAH-36 |
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8
V58C2256324SA Rev. 1.4 August 2007
ProMOS TECHNOLOGIES
V58C2256324SA
Data Strobe and Data Mask
Operation at Burst Reads
The Data Strobes provide a 3-state output signal to the receiver circuits of the controller during a read burst. The data strobe signal goes
1 clock cycle low before data is driven by the DDR SDRAM and then toggles low to high and high to low till the end of the burst. The
CAS latency is specified to the first low to high transition. The edges of the Output Data signals and the edges of the data strobe signals
during a read are nominally coincident with edges of the input clock. The tolerance of these edges is specified by the parameters tAC
and tDQSCK and is referenced to the crossing point of the CLK and /CLK signal. The tDQSQ timing parameter describes the skew
between the data strobe edge and the output data edge.
The following table summarizes the mapping of DQSx and DMx signals to the data bus.
Mapping of DQSx and DMx
The minimum time during which the output data is valid is critical for the receiving device. This also applies to the Data Strobe DQS
during a read since it is tightly coupled to the output data. The parameters tQH and tDQSQ define the minimum output data valid window.
Prior to a burst of read data, given that the device is not currently in burst read mode, the data strobe signals transit from Hi-Z to a valid
logic low. This is referred to as the data strobe
read preamble
tRPRE. This transition happens one clock prior to the first edge of valid
data.
Once the burst of read data is concluded, given that no subsequent burst read operation is initiated, the data strobe signals transit from
a valid logic low to Hi-Z. This is referred to as the data strobe read postamble
tRPST.
DQS Timing for Read
data strobe signal
data mask signal
Controlled data bus
DQS0
DM0
DQ7 .. DQ0
DQS1
DM1
DQ8 .. DQ15
DQS2
DM2
DQ16 .. DQ23
DQS3
DM3
DQ24 .. DQ31
DQx
CLK,
/CLK
DQS
"Preamble"
"Postamble"
VIH
VTT
VIL
t
RPRE
t
RPST
D
D+1
D+2
D+3
VIH
VTT
VIL
t
DQSQ
t
AC
T0
T1
T2
T3
T4
VIH
VIL
t
CH
t
CL
t
CK
t
DQSCK
t
HP
t
QH
t
QHS
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