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參數(shù)資料
| 型號： | V58C2256324SAH-36 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.55 ns, PBGA144 |
| 封裝： | ROHS COMPLIANT, BGA-144 |
| 文件頁數(shù)： | 37/37頁 |
| 文件大?。?/td> | 370K |
| 代理商： | V58C2256324SAH-36 |
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V58C2256324SA Rev. 1.4 August 2007
ProMOS TECHNOLOGIES
V58C2256324SA
Operation at Burst Write
During a write burst, control of the data strobe is driven by the memory controller. The DQSx signals are nominally centered with respect
to data and data mask. The tolerance of the data and data mask edges versus the data strobe edges during writes are specified by the
setup and hold time parameters of data (tQDQSS & tQDQSH) and data mask (tDMDQSS & tDMDQSH). The input data is masked in the
same cycle when the corresponding DMx signal is high (i.e. the DMx mask to write latency is zero.)
DQS and DM Timing at Write
Prior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal (DQSx) transits from Hi-
Z to a valid logic low. This is referred to as the data strobe Write Preamble. Once the burst of write data is concluded, given that no
subsequent burst write operation is initiated, the data strobe signal (DQSx) transits from a valid logic low to Hi-Z. This is referred to as
the data strobe W rite Postamble, tWPST. For DDR SDRAM, data is written with a delay which is defined by the parameter tDQSS (DDR
write latency). This is different than the single data rate SDRAM where data is written in the same cycle as the Write command is issued.
DQS Pre/Postamble at Write
Q+2
Q+4
Q+1
DQSx
VIH
VTT
VIL
DMx
VIH
VTT
VIL
t
DMDQSS
t
DMDQSS
t
DMDQSH
t
DMDQSH
t
QDQSH
t
QDQSH
DQx
Q
+3
VIH
VTT
VIL
t
QDQSS
t
QDQSS
Input Data masked
CLK,
/CLK
VIH
VIL
WR
DQSx
VIH
VTT
VIL
DQx
Q
Q+1
Q+2
Q+3
VIH
VTT
VIL
t
DQSS
t
WPREH
t
WPRES
t
WPST
"Preamble"
"Postamble"
Q
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