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參數(shù)資料
| 型號(hào)： | V58C2256324SAH-36 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.55 ns, PBGA144 |
| 封裝： | ROHS COMPLIANT, BGA-144 |
| 文件頁數(shù)： | 13/37頁 |
| 文件大小： | 370K |
| 代理商： | V58C2256324SAH-36 |
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V58C2256324SA Rev. 1.4 August 2007
ProMOS TECHNOLOGIES
V58C2256324SA
Read Concurrent Auto Precharge
Concurrent Read Auto Precharge Support
Note: This table is for the case of Burst Length = 4, CAS Latency =3 and tWR=2 clocks
When READ with Auto Precharge is asserted, new commands can be asserted at T4,T5 and T6 as shown in Table
An Interrupt of a running READ burst with Auto Precharge i.e. at T4 and T5 to the same bank with another READ+AP command is
allowed, it will extend the begin of the internal Precharge operation to the last READ+AP command.
Interrupts of a running READ burst with Auto Precharge i.e. at T4 are not allowed when doing concurrent command to another active
bank. ACTIVATE or PRECHARGE commands to another bank are always possible while a READ with Auto Precharge operation is in
progress.
Asserted
Command
For same Bank
For different Bank
T4
T5
T6
T4
T5
T6
READ
NO
YES
READ+AP
YES
NO
YES
ACTIVATE
NO
YES
PRECHARGE
YES
NO
YES
CLK
BANK A
ACTIVATE
Command
NOP
READ A
+ AP
NOP
Burst length = 4
DQSx
DQx
D-out
0
D-out
1
D-out
2
D-out
3
CAS latency = 3
CL = 3
Begin of
Auto Precharge
BL / 2
NOP
T0
T1
T2
T3
T4
T5
T6
T7
T8
t RCD(min)
t RAS(min)
t RP
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