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| 型號： | USB-EA-CONVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 61/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | SUPPORT BOARD ADUC8XX |
| 標準包裝： | 1 |
| 類型： | 仿真器 |
| 適用于相關產(chǎn)品： | ADuC8xx |
| 所含物品： | 模塊 |
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REV. B
ADuC824
–64–
As an alternative to providing two separate power supplies, AVDD
quiet by placing a small series resistor and/or ferrite bead between
it and DVDD, and then decoupling AVDD separately to ground. An
example of this configuration is shown in Figure 51. With this
configuration other analog circuitry (such as op amps, voltage
reference, etc.) can be powered from the AVDD supply line as well.
DVDD
48
34
20
ADuC824
5
6
AGND
AVDD
0.1 F
10 F
DGND
35
21
47
0.1 F
–
+
DIGITAL SUPPLY
10 F
1.6
BEAD
Figure 51. External Single Supply Connections
Notice that in both Figure 50 and Figure 51, a large value (10
F)
reservoir capacitor sits on DVDD and a separate 10
F capacitor
sits on AVDD. Also, local small-value (0.1
F) capacitors are
located at each VDD pin of the chip. As per standard design prac-
tice, be sure to include all of these capacitors, and ensure the
smaller capacitors are closest to each AVDD pin with trace lengths
as short as possible. Connect the ground terminal of each of these
capacitors directly to the underlying ground plane. Finally, it
should also be noticed that, at all times, the analog and digital
ground pins on the ADuC824 should be referenced to the same
system ground reference point.
Power Consumption
The “CORE” values given represent the current drawn by DVDD,
while the rest (“ADC,” and “DAC”) are pulled by the AVDD pin
and can be disabled in software when not in use. The other
on-chip peripherals (watchdog timer, power supply monitor, etc.)
consume negligible current and are therefore lumped in with the
“CORE” operating current here. Of course, the user must add
any currents sourced by the parallel and serial I/O pins, and that
sourced by the DAC, in order to determine the total current
needed at the ADuC824’s supply pins. Also, current draw from
the DVDD supply will increase by approximately 5 mA during
Flash/EE erase and program cycles
Power-Saving Modes
Setting the Idle and Power-Down Mode bits, PCON.0 and
PCON.1 respectively, in the PCON SFR described in Table II,
allows the chip to be switched from normal mode into idle mode,
and also into full power-down mode.
In idle mode, the oscillator continues to run, but the core clock
generated from the PLL is halted. The on-chip peripherals con-
tinue to receive the clock, and remain functional. The CPU status
is preserved with the stack pointer, program counter, and all other
internal registers maintain their data during idle mode. Port pins
and DAC output pins also retain their states, and ALE and
PSEN outputs go high in this mode. The chip will recover from
idle mode upon receiving any enabled interrupt, or on receiving
a hardware reset.
In power-down mode, both the PLL and the clock to the core
are stopped. The on-chip oscillator can be halted or can continue
to oscillate depending on the state of the oscillator power-down
bit (OSC_PD) in the PLLCON SFR. The TIC, being driven
directly from the oscillator, can also be enabled during power-
down. All other on-chip peripherals however, are shut down.
Port pins retain their logic levels in this mode, but the DAC output
goes to a high-impedance state (three-state) while ALE and
PSEN outputs are held low. During full power-down mode,
the ADuC824 consumes a total of 5
A typically. There are five
ways of terminating power-down mode:
Asserting the RESET Pin (#15)
Returns to normal mode all registers are set to their default state
and program execution starts at the reset vector once the Reset
pin is de-asserted.
Cycling Power
All registers are set to their default state and program execution
starts at the reset vector.
Time Interval Counter (TIC) Interrupt
Power-down mode is terminated and the CPU services the TIC
interrupt, the RETI at the end of the TIC Interrupt Service
Routine will return the core to the instruction after that which
enabled power down.
I
2C or SPI Interrupt
Power-down mode is terminated and the CPU services the I
2C/
SPI interrupt. The RETI at the end of the ISR will return the
core to the instruction after that which enabled power down. It
should be noted that the I
2C/SPI power down interrupt enable
bit (SERIPD) in the PCON SFR must first be set to allow this
mode of operation.
INT0 Interrupt
Power-down mode is terminated and the CPU services the
INT0 interrupt. The RETI at the end of the ISR will return the
core to the instruction after that which enabled power-down. It
should be noted that the
INT0 power-down interrupt enable bit
(INT0PD) in the PCON SFR must first be set to allow this
mode of operation.
Grounding and Board Layout Recommendations
As with all high resolution data converters, special attention must
be paid to grounding and PC board layout of ADuC824-based
designs in order to achieve optimum performance from the ADCs
and DAC.
Although the ADuC824 has separate pins for analog and digital
ground (AGND and DGND), the user must not tie these to two
separate ground planes unless the two ground planes are con-
nected together very close to the ADuC824, as illustrated in the
simplified example of Figure 52a. In systems where digital and
analog ground planes are connected together somewhere else
(at the system’s power supply for example), they cannot be con-
nected again near the ADuC824 since a ground loop would result.
In these cases, tie the ADuC824’s AGND and DGND pins all
to the analog ground plane, as illustrated in Figure 52b. In systems
with only one ground plane, ensure that the digital and analog
components are physically separated onto separate halves of the
board such that digital return currents do not flow near analog
circuitry and vice versa. The ADuC824 can then be placed between
the digital and analog sections, as illustrated in Figure 52c.
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