
562
SAM G51 [DATASHEET]
11209C–ATARM–20-Dec-13
Figure 27-9.
Master Write with One Byte Internal Address and Multiple Data Bytes
27.7.3.5
Master Receiver Mode
Master receiver mode is not available if high-speed mode is selected.
The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit
slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case
(MREAD = 1 in TWIHS_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line
(HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this
clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the
master sends an acknowledge condition to notify the slave that the data has been received except for the last data (see
Figure 27-10). When the RXRDY bit is set in the status register, a character has been received in the receive-holding
register (TWIHS_RHR). The RXRDY bit is reset when reading the TWIHS_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be
with or without internal address (IADR), the STOP bit must be set after the next-to-last data received (same condition
If the receive holding register (TWIHS_RHR) is full (RXRDY high) and the master is receiving data, the serial clock line
will be tied low before receiving the last bit of the data and until the TWIHS_RHR is read. Once the TWIHS_RHR is read,
the master will stop stretching the serial clock line and end the data reception, see
Figure 27-12.Warning: When receiving multiple bytes in master read mode, if the next-to-last access is not read (the RXRDY flag
remains high), the last access will not be completed until TWIHS_RHR is read. The last access stops on the next-to-last
bit (clock stretching). When the TWIHS_RHR is read there is only half a bit period to send the STOP bit (or START bit)
command, else another read access might occur (spurious access).
A possible workaround is to raise the STOP bit (or START bit) command before reading the TWIHS_RHR on the next-to-
last access (within IT handler).
A
DATA n
A
S
DADR
W
DATA n+1
A
P
DATA n+2
A
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1)
Write THR (Data n+2)
Last data sent
STOP command performed
(by writing in the TWIHS_CR)
TWD
IADR
A
TWCK