
555
SAM G51 [DATASHEET]
11209C–ATARM–20-Dec-13
27.
Two-Wire Interface (TWIHS)
27.1
Description
The Atmel Two-wire Interface (TWIHS) interconnects components on a unique two-wire bus, made up of one clock line
and one data line with speeds of up to 400 Kbits per second in fast mode and up to 3.4 Mbits per second in high-speed
slave mode only, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial
EEPROM and IC-compatible devices, such as a Real-Time Clock (RTC), Dot Matrix/Graphic LCD Controller and
temperature sensor. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple
master capability is supported.
Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.
lists the compatibility level of the Atmel Two-wire Interface in Master mode and a full I
2C compatible device.
Notes: 1.
10-bit support in Master mode only
2.
START + b000000001 + Ack + Sr
27.2
Embedded Characteristics
1 TWIHS
Compatible with Atmel Two-wire Interface Serial Memory and IC Compatible Devices
(1)One, Two or Three Bytes for Slave Address
Sequential Read/Write Operations
Master and Multi-Master Operation (Standard and Fast Mode Only)
Slave Mode Operation (Standard, Fast and High-Speed Mode)
Bit Rate: Up to 400 Kbit/s in Fast Mode and 3.4 Mbit/s in High-Speed Mode (Slave Only)
General Call Supported in Slave Mode
SMBUS Quick Command Supported in Master Mode
Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers
One Channel for the Receiver, One Channel for the Transmitter
Register Write Protection
Note:
1.
See 
Table 27-1 for details on compatibility with IC Standard.
Table 27-1.
Atmel TWI Compatibility with I2C Standard
I2C Standard
Atmel TWI
Standard Mode Speed (100 kHz)
Supported
Fast Mode Speed (400 kHz)
Supported
High-speed Mode (Slave only, 3.4 MHz)
Supported
7- or 10-bi
t(1) Slave Addressing
Supported
Not Supported
Repeated Start (Sr) Condition
Supported
ACK and NACK Management
Supported
Input Filtering
Supported
Slope Control
Not Supported
Clock Stretching
Supported
Multi Master Capability
Supported