參數(shù)資料
型號(hào)： UPD62AMC-XXX-5A4-A
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝： 0.300 INCH, PLASTIC, SSOP-20
文件頁(yè)數(shù)： 62/62頁(yè)
文件大小： 272K
代理商： UPD62AMC-XXX-5A4-A
9
PD62A
Data Sheet U14474EJ2V0DS00
2. INTERNAL CPU FUNCTIONS
2.1 Program Counter (PC): 10 Bits
This is a binary counter that holds the address information of the program memory.
Figure 2-1. Program Counter Configuration
PC9
PC0
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC
The program counter contains the address of the instruction that should be executed next. Normally, the counter
contents are automatically incremented in accordance with the instruction length (byte count) each time an
instruction is executed.
However, when executing JUMP instructions (JMP, JC, JNC, JF, JNF), the program counter contains the jump
destination address written in the operand.
When executing the subroutine call instruction (CALL), the call destination address written in the operand is
entered in the PC after the PC contents at the time are saved in the address stack register (ASR).
If the return
instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to
the PC.
When reset, the value of the program counter becomes “000H”.
2.2 Stack Pointer (SP): 1 Bit
This is a 1-bit register which holds the status of the address stack register.
The stack pointer contents are incremented when the call instruction (CALL) is executed; they are decremented
when the return instruction (RET) is executed.
When reset, the stack pointer contents are cleared to 0.
When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is hung up and a system reset
signal is generated, and the PC becomes “000H”.
As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer
by means of a program.
2.3 Address Stack Register (ASR (RF)): 10 Bits
The address stack register saves the return address of the program after a subroutine call instruction is executed.
The low-order 8 bits are configured as RAM that is also used as the data memory RF. The register holds the
ASR value even after RET is executed.
When reset, it holds the previous data (undefined on power application).
Caution If RF is accessed as data memory, the high-order 2 bits of the ASR become undefined.
Figure 2-2.
Address Stack Register Configuration
ASR9
ASR8
ASR7
ASR6
ASR5
ASR4
ASR3
ASR2
ASR1
ASR0
ASR
RF
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