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參數(shù)資料
| 型號： | UPD62AMC-XXX-5A4-A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 33/62頁 |
| 文件大?。?/td> | 272K |
| 代理商： | UPD62AMC-XXX-5A4-A |
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39
PD62A
Data Sheet U14474EJ2V0DS00
9.5 Input/Output Instructions
IN A, P0n
IN A, P1n
<1> Instruction code:
1 111 P4 11 P2 P1 P0
<2> Cycle count:
1
<3> Function:
(A)
← (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY
← 0
The port Pmn data is loaded (read) onto the accumulator.
OUT P0n, A
OUT P1n, A
<1> Instruction code:
0 010 P4 11 P2 P1 P0
<2> Cycle count:
1
<3> Function:
(Pmn)
← (A) m = 0, 1 n = 0, 1, 3, 4
The accumulator contents are transferred to port Pmn to be latched.
ANL A, P0n
ANL A, P1n
<1> Instruction code:
1 101 P4 11 P2 P1 P0
<2> Cycle count:
1
<3> Function:
(A)
← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY
← A3 Pmn
The accumulator contents and the port Pmn contents are ANDed and the results are entered in the
accumulator.
ORL A, P0n
ORL A, P1n
<1> Instruction code:
1 110 P4 11 P2 P1 P0
<2> Cycle count:
1
<3> Function:
(A)
← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY
← 0
The accumulator contents and the port Pmn contents are ORed and the results are entered in the
accumulator.
XRL A, P0n
XRL A, P1n
<1> Instruction code:
1 010 P4 11 P2 P1 P0
<2> Cycle count:
1
<3> Function:
(A)
← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY
← A3 Pmn
The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered
in the accumulator.
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