參數(shù)資料
型號(hào)： TXC-02050-AIPL
廠商： Electronic Theatre Controls, Inc.
英文描述： MRT Device 6-,8-,34-Mbit Line Interface TXC-0250
中文描述： 捷運(yùn)設(shè)備6 - ，8 - ,34 - Mbit的線路接口晶技- 0250
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 134K
代理商： TXC-02050-AIPL
- 7 -
MRT
TXC-02050-MB
Ed. 3, April 1994
Pins With External Components
EQB1
EQB0
27
28
I
I
CMOSr
Equalizer Bit 1:
MSB of equalizer setting.
Equalizer Bit 0:
LSB of equalizer setting. Equalization
is as follows for 34 Mbit/s operation:
EQB1
EQB0 CABLE EQUALIZATION
√
f *
1 1 0dB< cable <3.5dB
1 0 2.6dB<cable<8dB
0 0 6dB<cable<9.9dB
0 1 8.6dB<cable<13.2dB
For 8 or 6 Mbit/s operation:
1 1 0dB< cable< 4.1dB
1 0 2.5dB<cable<6.5dB
* f = 1/2 the bit rate
TXAIS
43
I
CMOSr
Transmit AIS:
When TXAIS is low, the MRT sends an
AIS (all ones signal) for the line side transmit output
data. The terminal side transmit data path is disabled.
The reference clock (DCK) provides the clock required
for generating AIS.
Symbol
Pin No.
I/O/P
Type
Name/Function
VCOC
7
I/O
Analog
Voltage Controlled Oscillator Capacitor:
For 6, 8,
and 34 Mbit/s operation, a 470
±
5%, 1/8 watt resis-
tor is connected in series with a 0.1
μ
F
±
10% capaci-
tor to ground. These components are used in the
phase-locked loop filter.
PLLC
17
I/O
Analog
Phase-Locked Loop Capacitor:
0.1
μ
F
±
10%
ceramic disk capacitor connected to ground.
AGFIL
22
I/O
Analog
Automatic Gain Filter:
For 6/8 MHz mode, 0.01
μ
F
±
10% ceramic disk capacitor connected to ground. For
34 Mbit/s mode, open.
Symbol
Pin No.
I/O/P
Type
Name/Function
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TXC-02050AIPL/S 制造商:Transwitch Corporation 功能描述:
TXC-02050C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MRT Device 6-,8-,34-Mbit Line Interface TXC-0250C
TXC-02050CIPL 制造商:Transwitch Corporation 功能描述:MRT Device 44-Pin PLCC
TXC-02050-CIPL 制造商:Transwitch Corporation 功能描述:DATACOM, HDB3 ENCODER/DECODER, PQCC44
TXC0-2200-003 制造商:Vishay Dale 功能描述:
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