參數(shù)資料
型號(hào)： TXC-02050-AIPL
廠商： Electronic Theatre Controls, Inc.
英文描述： MRT Device 6-,8-,34-Mbit Line Interface TXC-0250
中文描述： 捷運(yùn)設(shè)備6 - ，8 - ,34 - Mbit的線路接口晶技- 0250
文件頁(yè)數(shù)： 3/28頁(yè)
文件大小： 134K
代理商： TXC-02050-AIPL
- 3 -
MRT
TXC-02050-MB
Ed. 3, April 1994
Two Terminal Side interfaces are provided, a positive and negative rail (RP and RN) or NRZ (RD) interface.
The selection is determined by the state placed on the signal lead labeled PNENB. When a low is applied to
the signal lead, the HDB3 Decoder and HDB3 Encoder Blocks are bypassed, and the terminal side I/O is a
positive and negative rail interface. When a high is applied to the signal lead, an NRZ interface is provided.
Data is clocked out of the MRT on negative edges of the clock signal (CLKO). Receive data and the clock sig-
nals are disabled, and forced to a high impedance state by placing a low on the receive disable lead (RXDIS).
For a receive positive and negative rail interface, an inverted clock (CLKO) is also provided.
The terminal side interface for the transmitter can either be positive and negative rail (TP and TN) or NRZ (TD)
data depending on the state of the common control lead PNENB. Data is clocked into the MRT on positive
transitions of the clock signal (CLKI). The input clock is monitored for the loss of clock. When the input clock
remains high or low, TXLOC will be set low. The MRT also provides the capability to generate and insert AIS
(all ones signal), independent of the transmit data. A low placed on the TXAIS lead enables the transmit AIS
generator.
Two loopbacks are provided, transmit loopback and receive loopback. Transmit loopback connects the data
path from the transmitter output driver stage to the clock recovery, and disables the external receiver input.
Transmit loopback is activated by placing a low on the LBKTX signal lead.
Receive loopback connects the receive data path to the transmit output circuits and disables the transmit input.
Receive loopback is activated by placing a low on the LBKRX signal lead.
For 6 Mbps operation, the MRT should be operated in the P and N rail mode, bypassing the HDB3 Decoder/
Encoder.
PIN DIAGRAM
Figure 2. MRT Pin Diagram With Names and Numbers
MRT PIN DIAGRAM
(Top View)
2
4
6
8
10
12
14
16
1
2
2
2
2
2
30
32
34
36
38
4
4
4
PLLC
GND
CLKO
CLKO
RP/RD
RN
GND
VDD
DCK
PNENB
VCOC
DI1
DI2
GNDA
GND
TNO
TPO
VDD
GND
VDD
CLKI
GND
T
T
V
T
G
G
T
R
B
L
G
E
E
L
L
L
V
A
R
R
C
V
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TXC-02050AIPL/S 制造商:Transwitch Corporation 功能描述:
TXC-02050C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MRT Device 6-,8-,34-Mbit Line Interface TXC-0250C
TXC-02050CIPL 制造商:Transwitch Corporation 功能描述:MRT Device 44-Pin PLCC
TXC-02050-CIPL 制造商:Transwitch Corporation 功能描述:DATACOM, HDB3 ENCODER/DECODER, PQCC44
TXC0-2200-003 制造商:Vishay Dale 功能描述:
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