參數(shù)資料
型號(hào): TXC-02050-AIPL
廠(chǎng)商: Electronic Theatre Controls, Inc.
英文描述: MRT Device 6-,8-,34-Mbit Line Interface TXC-0250
中文描述: 捷運(yùn)設(shè)備6 - ,8 - ,34 - Mbit的線(xiàn)路接口晶技- 0250
文件頁(yè)數(shù): 14/28頁(yè)
文件大?。?/td> 134K
代理商: TXC-02050-AIPL
- 14 -
MRT
TXC-02050-MB
Ed. 3, April 1994
Figure 8. P and N Rail Transmit Input
t
CYC
Note 1: CLKI symmetry is measured about the 1.4VDC threshold.
Note 2: The clock input can be 6, 8, or 34 MHz (refer to page 5).
Figure 9. P and N Rail Receive Timing
t
CYC
Note 1: CLKO symmetry is measured about the 50% amplitude point.
Note 2: The clock output can be 6, 8, or 34 MHz (refer to page 4).
Parameter
Symbol
Min
Typ
Max
Unit
CLKI clock period
t
CYC
--
Note 2
ns
CLKI duty cycle (t
PWH
/t
CYC
)
TP,TD & TN set-up time to CLKI
45
55
%
t
SU
t
H
3
ns
TP,TD & TN hold time after CLKI
2
ns
Parameter
Symbol
Min
Typ
Max
Unit
CLKO clock period
t
CYC
--
Note 2
ns
CLKO duty cycle (t
PWH
/t
CYC
)
CLKO output delay after CLKO
45
55
%
t
OD(1)
t
OD(2)
2
ns
RP, RD and RN output delay after CLKO
-5
6
ns
DATA
VALID
DATA
VALID
DATA
VALID
CLKI
1.4V
TP,TD
t
SU
t
PWH
t
H
DATA
VALID
DATA
VALID
DATA
VALID
TN
CLKO
RP,RD
t
PWH
t
OD(1)
t
OD(2)
RN
CLKO
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