參數(shù)資料
型號: TXC-02050-AIPL
廠商: Electronic Theatre Controls, Inc.
英文描述: MRT Device 6-,8-,34-Mbit Line Interface TXC-0250
中文描述: 捷運設(shè)備6 - ,8 - ,34 - Mbit的線路接口晶技- 0250
文件頁數(shù): 16/28頁
文件大?。?/td> 134K
代理商: TXC-02050-AIPL
- 16 -
MRT
TXC-02050-MB
Ed. 3, April 1994
OVERVIEW
Line Side Input Impedance
The input impedance of the MRT is a function of the state of the LOW lead and the operating rate. Table 1 lists
the input impedance of the MRT at the operating line rates (which are 1/2 the bit rates).
Line Side Input Sensitivity
The input voltage sensitivity of the MRT depends on the state of the LOW lead as shown in Table 2 below.
Line Side Input Circuit
The circuit shown in Figure 11 illustrates the component required for operating the MRT device for 34368,
8448 or 6312 kbit/s. The transformer should have a frequency response of 0.2 to 80 MHz with an insertion loss
of 1 dB, maximum. TranSwitch recommends the use of a Coilcraft transformer (part no. WB-1010) or equiva-
lent). This gives return loss and isolation voltage values that meet or exceed requirements.
Figure 11. Line Side Input Circuit
Line Side Output Characteristics
The line side output of the MRT switches from “rail to rail” on both of its output leads, TPO and TNO. This pro-
vides the maximum voltage swing, and makes the output voltage depend on the +5 volt power supply input to
the chip. The external circuit design must therefore be done with care in order to assure the meeting of the
amplitude requirements.
Table 1. MRT Input Impedance
Condition
Minimum Input Impedance, | Z |
LOW = 1, line rate = 17184 kbit/s
1260 ohms
LOW = 0, line rate = 4224 kbit/s
2390 ohms
LOW = 0, line rate = 3156 kbit/s
3670 ohms
Table 2. MRT Input Sensitivity
LOW Lead
Input Sensitivity (peak volts)
Min Max
0
0.5 2.7 (6 & 8 Mbit/s)
1
0.15 1.1 (34 Mbit/s)
TXC-02050
MRT
Device
1 : 1
Receive
Data
Input
10/6.3
10/6.3
0.1
0.1
75
5%
+
+
29
30
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相關(guān)代理商/技術(shù)參數(shù)
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