參數(shù)資料
型號: TXC-02050-AIPL
廠商: Electronic Theatre Controls, Inc.
英文描述: MRT Device 6-,8-,34-Mbit Line Interface TXC-0250
中文描述: 捷運(yùn)設(shè)備6 - ,8 - ,34 - Mbit的線路接口晶技- 0250
文件頁數(shù): 4/28頁
文件大小: 134K
代理商: TXC-02050-AIPL
- 4 -
MRT
TXC-02050-MB
Ed. 3, April 1994
PIN DESCRIPTIONS
Power Supply and Ground
*Note: I = Input; O = Output; P = Power
Line Side I/O
Terminal Side I/O
Symbol
Pin No.
I/O/P*
Type
Name/Function
VDD
10,18,35,
37,42
P
VDD:
5-volt supply,
±
5%.
GND
1,6,11,16,32,
36,39,44
P
Ground:
0 volts reference.
VAGC
23
P
AGC VDD:
Isolate from VDD using 1N914 or 1N4148
diode.
GNDA
31
P
AGC Groun
d: 0 volts reference.
Symbol
Pin No.
I/O/P
Type
Name/Function
DI1
29
I
Analog
Data In 1:
HDB3 or B8ZS encoded bipolar receive
data input.
DI2
30
O
Analog
Data In 2:
DC Voltage Reference for Data Input DI1.
The MRT uses an internally generated voltage refer-
ence as an AC ground for the received data input. An
external 0.1
μ
F capacitor, in parallel with a 10
μ
F/6.3 V
tantalum capacitor, is connected between this pin and
ground. No other connection should be made to this
pin.
TNO
33
O
TTL24mA
Transmit Negative Out:
Line transmit negative; out-
put is an active low.
TPO
34
O
TTL24mA
Transmit Positive Out:
Line transmit positive; output
is an active low.
Symbol
Pin No.
I/O/P
Type
Name/Function
RN
12
O
TTL4mA
Receive Negative:
When PNENB is low, the HDB3
codec is bypassed and N-rail (RN) data is provided on
this pin. When PNENB is high, the output is forced to
a high impedance state.
RP/RD
13
O
TTL4mA
Receive Positive/Receive Data:
When PNENB is
low, the HDB3 codec is bypassed and P-Rail (RP)
data is provided on this pin. When PNENB is high,
NRZ data (RD) is provided.
CLKO
14
O
CMOS8mA
Clock Out Inverted:
Receive inverted clock output.
Positive and negative rail receive data is clocked out
on the rising edge. Disabled in the NRZ mode.
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