- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385038 > TXC-02050-AIPL (Electronic Theatre Controls, Inc.) MRT Device 6-,8-,34-Mbit Line Interface TXC-0250 PDF資料下載
參數(shù)資料
| 型號： | TXC-02050-AIPL |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MRT Device 6-,8-,34-Mbit Line Interface TXC-0250 |
| 中文描述： | 捷運(yùn)設(shè)備6 - ，8 - ,34 - Mbit的線路接口晶技- 0250 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 134K |
| 代理商： | TXC-02050-AIPL |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
- 6 -
MRT
TXC-02050-MB
Ed. 3, April 1994
MRT Control Leads
Symbol
Pin No.
I/O/P
Type
Name/Function
RXAIS
3
I
CMOSr
Receive Alarm Indication Signal:
When RXAIS is
low, the MRT generates AIS (all ones signal) for the
terminal side receive output data. The line side
receive data path is disabled. The reference clock
(DCK) provides the clock source required for generat-
ing AIS.
BERCK
4
I
TTLr
Bit Error Rate Clock:
This clock establishes the time
base for estimating the coding violation error rate. For
34 Mbit/s operation the clock frequency must be 6
kHz, and for 8 Mbit/s operation the clock frequency
must be 1.5 kHz. This pin should be left open for P
and N mode operation.
PNENB
8
I
CMOSr
P And N Enable:
When PNENB is low, the P and N
rail interface is enabled, and the HDB3 codec is
bypassed. When PNENB is high, the terminal side I/O
data is NRZ and the HDB3 codec is enabled. This pin
must be held low for 6 Mbit/s operation.
DCK
9
I
TTL
Reference Clock:
Operating frequency reference
clock. For receive signal clock recovery,
±
200 ppm
frequency accuracy is adequate. If the transmit and
receive AIS features are used, the frequency accuracy
must be
±
20 ppm for 34368 kbit/s and
±
30 ppm for
8448 and 6312 kbit/s operation. The duty cycle
requirement for this clock signal is 50%
±
5% as mea-
sured at the 1.4V TTL threshold level.
RXDIS
21
I
CMOSr
Receive Disable:
When RXDIS is low, the receive
side of the MRT is disabled and the RN, RP/RD,
CLKO and CLKO output leads are forced to a high
impedance state.
LBKRX
24
I
CMOSr
Loopback Receive:
When LBKRX is low, the MRT
loops back receive data as transmit data. The receive
data is also sent to the terminal side, but the transmit
data input on the terminal side is disabled. (Note 1)
LBKTX
25
I
CMOSr
Loopback Transmit:
When LBKTX is low, the MRT
loops back transmit data as receive data. The transmit
data is sent on the line side, but the receive data input
on the line side is disabled. (Note 1)
LOW
26
I
CMOSr
Low Frequency:
When LOW is low, the MRT enables
equalization and input attenuator settings for 6312 or
8448 kbit/s operation. This lead also controls the clock
recovery high/low frequency range circuit.
Note 1: Setting
LBKTX
and
LBKRX
low simultaneously will cause invalid outputs at the receive terminal and transmit line
ports.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TXC100 | Single chip OOK/ASK/FSK Transmitter IC in the 300~450 MHz frequency range. |
| TXC101 | Multi-channel High data rate Programmable |
| TXC102 | Multi-channel High tae rate Programmable |
| TXD1005KASLPLNH | 1000 WATT AC/DC POWER SUPPLY |
| TXD1005LASLPLNH | 1000 WATT AC/DC POWER SUPPLY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TXC-02050AIPL/S | 制造商:Transwitch Corporation 功能描述: |
| TXC-02050C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MRT Device 6-,8-,34-Mbit Line Interface TXC-0250C |
| TXC-02050CIPL | 制造商:Transwitch Corporation 功能描述:MRT Device 44-Pin PLCC |
| TXC-02050-CIPL | 制造商:Transwitch Corporation 功能描述:DATACOM, HDB3 ENCODER/DECODER, PQCC44 |
| TXC0-2200-003 | 制造商:Vishay Dale 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。