
- 5 -
MRT
TXC-02050-MB
Ed. 3, April 1994
Alarm Signal Outputs
CLKO
15
O
CMOS8mA
Clock Out:
Receive clock output. Receive positive
and negative rail and NRZ data is clocked out on the
falling edge.
CLKI
38
I
TTLr
Clock In:
Transmit clock input for P and N rail and
NRZ data. Transmit data is clocked into the MRT on
the rising edge. This clock must have a frequency of
±
20 ppm for the 34368 kbit/s operation and
±
30 ppm
for the 6312/8448 kbit/s operation (ref: CCITT recom-
mendation G.703). The duty cycle requirement for this
clock signal is 50%
±
5%, measured at the 1.4V TTL
threshold level.
TP/TD
40
I
TTL
Transmit Positive/Transmit Data:
When PNENB is
low, the HDB3 codec is bypassed and transmit P-rail
(TP) data is applied to this pin. When PNENB is high,
NRZ transmit data (TD) is applied.
TN
41
I
TTL
Transmit Negative:
When PNENB is low, the HDB3
codec is bypassed and transmit N-Rail (TN) is applied
to this pin. When PNENB is high, this input is disabled.
Symbol
Pin No.
I/O/P
Type
Name/Function
TXLOC
2
O
TTL2mA
Transmit Loss Of Clock:
Active low output. A trans-
mit loss of clock alarm occurs when the transmit clock
input (CKLI) is stuck high or low for 20-32 clock cycles.
Recovery occurs on the first input clock transition.
LQLTY
5
O
TTL2mA
Line Quality:
This signal represents a gross estimate
of the line quality which is determined by counting
coding violations for 34 (8) Mbit/s operation. If the line
error rate exceeds a 10
-6
threshold during a 10 (40)
second interval, LQLTY goes active high. LQLTY is
active low when coding violations do not exceed the
10
-6
threshold in a 10 (40) second interval. The output
on this pin is only valid when the appropriate clock sig-
nal is applied to BERCK. It should be disregarded in
the P and N mode of operation.
CV
19
O
TTL2mA
Coding Violation:
Active high output. A coding viola-
tion pulse occurs when an HDB3 coding violation is
detected in the received line data input. A coding vio-
lation is not part of the HDB3 zero-substitution code. A
coding violation occurs because of noise or other
impairments affecting the line signal. The output of this
pin should be disregarded in the P and N mode.
RXLOS
20
O
TTL2mA
Receive Loss Of Signal:
Active low output. A receive
loss of signal occurs when the input data is zero for
20-32 clock cycles. Recovery occurs when the receive
signal returns.
Symbol
Pin No.
I/O/P
Type
Name/Function