參數(shù)資料
型號: TVP5145
英文描述: NTSC/PAL/SECAM/Component Digital Video Decoder With Macrovision(TM) Detection
中文描述: 的NTSC / PAL / SECAM制式/分量數(shù)字視頻解碼器通過Macrovision(TM)的檢測
文件頁數(shù): 49/92頁
文件大?。?/td> 525K
代理商: TVP5145
2
33
2.12.4 Miscellaneous Control Register
Address
03h
7
6
5
4
3
2
1
0
GPCL pin
function select
PALI pin and FID pin
function select
Y U/V output
enable
HSYN, VSYN, AVID,
FID, PALI output enable
Reserved
Vertical blanking
on/off
Clock output
enable
GPCL pin function select:
00 = GPCL is logic 0 output (default)
01 = GPCL is logic 1 output
10 = GPCL is vertical blank output. The vertical blanking on/off bit is used to activate the output.
11 = GPCL is external sync lock control input. All clocks and synchronization signals to assume nominal
values. The sync lock control input is active high.
PALI pin and FID pin function select:
0 = PALI outputs PAL indicator signal and pin FID outputs field ID signal (default)
1 = PALI outputs horizontal lock indicator (HLK) and pin FID outputs vertical lock indicator (VLK)
Y U/V output enable:
0 = Y U/V high impedance
1 = Y U/V active
This bit defaults to 0 after reset if terminal 28 (AVID) is pulled down during reset or defaults to 1 if terminal 28 (AVID)
is pulled up during reset.
Horizontal sync (HSYN), vertical sync (VSYN), active video indicator (AVID), PALI, and FID output enables:
0 = HSYN, VSYN, AVID, PALI, and FID are high-impedance
1 = HSYN, VSYN, AVID, PALI, and FID are active
This bit defaults to 0 after reset if terminal 28 (AVID) is pulled down during reset or defaults to 1 if terminal 28 (AVID)
is pulled up during reset.
Vertical blanking on/off:
0 = Vertical blanking off (default)
1 = Vertical blanking on
Clock output enable:
0 = SCLK and PCLK outputs are high-impedance
1 = SCLK and PCLK outputs are enabled (default)
Table 2
11. Digital Output Control
Terminal
24 (OEB)
Terminal 28
(AVID)
Register 03,
Bit 4 (TVPOE)
Register C2,
Bit 2 (VDPOE)
YUV Output
Notes
1
X
X
X
High impedance
At all times
0
1 during reset
X
X
Active after
reset
After reset and before YUV output enable bits are
programmed. TVPOE defaults to 1 and VDPOE is 1.
0
0 during reset
X
X
High impedance
after reset
After reset and before YUV output enable bits are
programmed. TVPOE defaults to 0 and VDPOE is 1.
0
X
0
X
High impedance
After both YUV output enable bits are programmed.
0
X
X
0
High impedance
After both YUV output enable bits are programmed.
0
X
1
1
Active
After both YUV output enable bits are programmed.
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