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參數(shù)資料
| 型號(hào)： | TVP5145 |
| 英文描述： | NTSC/PAL/SECAM/Component Digital Video Decoder With Macrovision(TM) Detection |
| 中文描述： | 的NTSC / PAL / SECAM制式/分量數(shù)字視頻解碼器通過Macrovision（TM）的檢測 |
| 文件頁數(shù)： | 40/92頁 |
| 文件大?。?/td> | 525K |
| 代理商： | TVP5145 |
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2
–
24
2.7.2.3 Latency
PHI accesses to indirect addresses 00h
–
8Fh require special consideration due to response latencies of up to 64
μ
s
for these addresses. Latency occurs between steps 1 and 2 for a read operation, and following step 2 for a write
operation. To avoid violating PHI cycle time requirements the host can poll the cycle complete bit in the PHI status
register following step 1 for a read or step 2 for a write. Alternatively, the cycle complete enable bit in the interrupt
enable register (indirect address C1h) can be set to generate an interrupt for the host when an access has been
completed.
PHI accesses to indirect addresses 90h
–
CFh occur with minimal latency and interrupts will not be generated for the
completion of access cycles to these addresses.
2.7.2.4 VBI FIFO
The VBI FIFO containing sliced VBI data can be read directly by the PHI host.
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read VBI FIFO
1
0
Data from FIFO
2.7.2.5 Interrupt Status Register A
Interrupt status register A provides the host with information regarding the source of an interrupt. After an interrupt
condition is set, it can be reset by writing a 1 to the appropriate bit in interrupt status register A. Section 2.12.51
contains a description of interrupt status register A.
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Access status/interrupt register
1
1
Data to/from interrupt status register A
2.7.2.6 Microprocessor Start by PHI
After hardware reset, the register 7Fh must be written with any data in order to start an operation of the TVP5145
device.
Write indirect register
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register address
0
0
0
1
1
1
1
1
1
1
Write to microprocessor start address = 7Fh
Step 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register data
0
1
Data to register
Any data written to 7Fh will start the TVP5145 device.
2.8
VBI Data Processor
The TVP5145 VBI data processor (VDP) slices various data services like teletext (WST, NABST), closed caption
(CC), wide screen signaling (WSS), VITC, and VPS. These services are acquired by programming the VDP to enable
a standard(s) in the vertical blank interval. The results are stored in a FIFO and/or registers. The teletext results are
stored in a FIFO only.
Table 2
–
6 lists a summary of the types of vertical blank interval data supported according to the video standard. It
supports both square pixel and ITU
–
R BT.601 sampling for each standard. The total of 26 standard modes and
2 custom modes are currently supported. One configuration for a standard mode consists of 15 bytes of data plus
1 fill byte. The custom modes are specified by the configuration data (in configuration RAM) when stored in the
locations that are designated as custom.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP5145EVM | 制造商:Texas Instruments 功能描述:TVP5145EVM - Bulk |
| TVP5145PFP | 功能描述:視頻 IC NTSC/PAL/SECAM/ Comp Dig Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5146 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL / SECAM 4 X 10 BIT DIGITAL VIDEO DECODER WITH MACROVISION DETECTION YPBPR/RGB INPUTS 5 LINE COMB FILTER AND SCART SUPPORT |
| TVP5146_12 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL/SECAM 4x10-Bit Digital Video Decoder With Macrovision?￡a Detection, YPbPr/RGB Inputs, 5-Line Comb Filter, and SCART Support |
| TVP5146EVM | 功能描述:視頻 IC 開發(fā)工具 TVP5146 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Boards 類型:YPbPr to RGBHV Converters 工具用于評(píng)估:LMH1251 工作電源電壓:5 V |
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