參數(shù)資料
型號： TVP5145
英文描述： NTSC/PAL/SECAM/Component Digital Video Decoder With Macrovision(TM) Detection
中文描述： 的NTSC / PAL / SECAM制式/分量數(shù)字視頻解碼器通過Macrovision（TM）的檢測
文件頁數(shù)： 28/92頁
文件大小： 525K
代理商： TVP5145
2
–
12
2.3
Clock Circuits
An internal line-locked phase-locked loop (PLL) generates the system and pixel clocks. A 14.318-MHz or 27-MHz
clock is required to drive the PLL. This may be input to the TVP5145 device at the TTL level on terminal 35 (XTAL1),
or a crystal of 14.318-MHz or 27-MHz frequency may be connected across terminals 35 and 36 (XTAL2). If a parallel
resonant circuit is used as shown in Figure 2
–
21, then the external capacitors must have the following relationship:
C
L1
= C
L2
= 2C
L
–
C
STRAY
,
where C
STRAY
is the terminal capacitance with respect to ground. Figure 2
–
21 shows the reference clock
configurations.
TVP5145
35
XTAL1
14.318-MHz or
27-MHz Crystal
36
XTAL2
TVP5145
35
XTAL1
36
XTAL2
CL1
CL2
14.318-MHz or
27-MHz TTL
Clock
Figure 2
–
21. Reference Clock Configurations
The TVP5145 device generates three signals PCLK, SCLK, and PREF used for clocking data. PCLK, the pixel clock,
can be used for clocking data in the 20-/16-bit 4:2:2 output formats. SCLK is at twice the PCLK frequency and may
be used for clocking data in the 10-/8-bit 4:2:2 as well as in ITU-R BT.656 formats. PREF is used as a clock qualifier
with SCLK to clock data in the 20-/16-bit 4:2:2 formats, or as an alternate pixel clock.
2.4
Genlock Control (GLCO) and Real-Time Control (RTC)
The frequency control word of the internal color subcarrier PLL and the subcarrier phase reset bit are transmitted via
terminal 31 (GLCO/RTC). The frequency control word is a 23-bit binary number. The frequency of the PLL can be
calculated from the following equation:
F
=
2
PLL
ctrl
23
sclk
F
F
x
where F
PLL
is the frequency of the PLL, F
ctrl
is the 23-bit PLL frequency control and F
sclk
is the frequency of the SCLK.
The selection between Genlock and RTC is controlled by the Genlock and RTC register described in Section 2.12.18.
2.4.1
GLCO Mode
Figure 2
–
22 shows the timing diagram of the GLCO mode. The upper 22 bits of the frequency control are used. A
write of 1 to bit 4 of the chrominance control register at host port subaddress 1Ah causes the subcarrier PLL phase
reset bit to be sent on the next scan line on GLCO. The active low reset bit occurs 7 SCLKs after the transmission
of the last bit of PLL frequency control. Upon the transmission of the reset bit, the phase of the TVP5145 internal
subcarrier PLL is reset to zero. A genlocking slave device can be connected to the GLCO terminal and uses the
information on GLCO to synchronize its internal color phase PLL.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP5145EVM 制造商:Texas Instruments 功能描述:TVP5145EVM - Bulk
TVP5145PFP 功能描述:視頻 IC NTSC/PAL/SECAM/ Comp Dig Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
TVP5146 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL / SECAM 4 X 10 BIT DIGITAL VIDEO DECODER WITH MACROVISION DETECTION YPBPR/RGB INPUTS 5 LINE COMB FILTER AND SCART SUPPORT
TVP5146_12 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL/SECAM 4x10-Bit Digital Video Decoder With Macrovision?￡a Detection, YPbPr/RGB Inputs, 5-Line Comb Filter, and SCART Support
TVP5146EVM 功能描述:視頻 IC 開發(fā)工具 TVP5146 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Boards 類型:YPbPr to RGBHV Converters 工具用于評估:LMH1251 工作電源電壓:5 V
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