
2
–
25
Table 2
–
6. Data Types Supported by the VDP
LINE MODE
REGISTER (D0h
–
FCh)
BITS [3:0]
SAMPLING
RATE (0Dh)
BIT 7
NAME
DESCRIPTION
0000b
0
WST SECAM S
Teletext, SECAM, Square
0000b
1
WST SECAM 6
Teletext, SECAM, ITU
–
R BT 601
0001b
0
WST PAL B S
Teletext, PAL, System B, Square
0001b
1
WST PAL B 6
Teletext, PAL, System B, ITU
–
R BT 601
0010b
0
WST PAL C S
Teletext, PAL, System C, Square
0010b
1
WST PAL C 6
Teletext, PAL, System C, ITU
–
R BT 601
0011b
0
WST, NTSC B S
Teletext, NTSC, System B, Square
0011b
1
WST, NTSC B 6
Teletext, NTSC, System B, ITU
–
R BT 601
0100b
0
NABTS, NTSC C S
Teletext, NTSC, System C, Square
0100b
1
NABTS, NTSC C 6
Teletext, NTSC, System C, ITU
–
R BT 601
0101b
0
NABTS, NTSC D S
Teletext, NTSC, System D (Japan), Square
0101b
1
NABTS, NTSC D 6
Teletext, NTSC, System D (Japan), ITU
–
R BT 601
0110b
0
CC, PAL/SECAM S
Closed Caption PAL/SECAM, Square
0110b
1
CC, PAL/SECAM 6
Closed Caption PAL/SECAM, ITU
–
R BT 601
0111b
0
CC. NTSC S
Closed Caption NTSC, Square
0111b
1
CC, NTSC 6
Closed Caption NTSC, ITU
–
R BT 601
1000b
0
WSS, PAL/SECAM S
Wide Screen signal, PAL/SECAM, Square
1000b
1
WSS, PAL/SECAM 6
Wide Screen signal, PAL/SECAM, ITU
–
R BT 601
1001b
0
WSS, NTSC S
Wide Screen signal, NTSC, Square
1001b
1
WSS, NTSC 6
Wide Screen signal, NTSC, ITU
–
R BT 601
1010b
0
VITC, PAL/SECAM S
Vertical Interval timecode, PAL/SECAM, Square
1010b
1
VITC, PAL/SECAM 6
Vertical Interval timecode, PAL/SECAM, ITU
–
R BT 601
1011b
0
VITC, NTSC S
Vertical Interval timecode, NTSC, Square
1011b
1
VITC, NTSC 6
Vertical Interval timecode, NTSC, ITU
–
R BT 601
1100b
0
VPS, PAL S
Video Program System, PAL, Square
1100b
1
VPS, PAL 6
Video Program System, PAL, ITU
–
R BT 601
1101b
Custom
Custom
1110b
Custom
Custom
1111b
x
Active Video
Active Video/Full Field
At powerup the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with the
lookup table (see Section 2.12.54). This is done through port address C3h. Each read from or write to this address
will auto increment an internal counter to the next RAM location. To access the VDP
–
CRAM, the line mode registers
(D0h
–
FCh) must be programmed with FFh to avoid a conflict with the microprocessor and the VDP in both writing
and reading. Full field mode must also be disabled.
Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Theoretically, each line can be any VBI mode
because the VDP processes VBI data on a line-by-line basis. When changing modes, the VDP must allow the current
transaction to complete through the delays of the VDP before loading the configuration for the next line into the VDP
core. It must also complete loading the configuration before the next line starts processing. The switch pixel number
is set through registers CBh and CCh. The default values of CBh and CCh work for all standard modes.
Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h
–
AFh, both of which
are available from the host port.