參數(shù)資料
型號： TVP5145
英文描述： NTSC/PAL/SECAM/Component Digital Video Decoder With Macrovision(TM) Detection
中文描述： 的NTSC / PAL / SECAM制式/分量數(shù)字視頻解碼器通過Macrovision（TM）的檢測
文件頁數(shù)： 39/92頁
文件大?。?/td> 525K
代理商： TVP5145
2
–
23
Terminal 80 (INTREQ) is a nominally open drain terminal used to signal interrupts to the host controller. This terminal
may be configured as a conventional CMOS I/O buffer (non-open drain) if desired using the interrupt configuration
register at subaddress C2h. Contention is possible if multiple devices are connected to the INTREQ signal and it is
configured in non-open drain mode.
VC0 (DTACK/READY) is in a high-impedance state when VC3 (CS) is not asserted.
2.7.2.1 PHI Register Mapping
The PHI module contains only four registers that are directly accessible to the host (see Figure 2
–
30). The address
register holds an indirect address for internal control register access. When the host accesses the data register, the
PHI module reads or writes the internal register selected by the indirect address register. Two other registers are
provided for direct access. The FIFO register provides direct access to the VBI FIFO. The other direct access register
is the interrupt status register A (C0h). This register contains the state of the interrupt sources.
00
Internal Control
Address
A[1:0]
01
Data
10
VBI FIFO
11
Interrupt Status
Register A
Figure 2
–
30. PHI Address Register Map
Normally read or write operations require two accesses. To read the VBI FIFO register, set A[1:0] = 10b and perform
a read cycle. The FIFO read data will be placed on the D[7:0] bus. To read/write interrupt status register A, set
A[1:0] = 11b and perform the read/write cycle. The read/write data will be appropriately multiplexed to/from the
external data bus.
2.7.2.2 PHI Read/Write Operation
All PHI accesses except for the VBI FIFO and the status/interrupt register require a two-step operation. To access
an indirect register the desired internal address must first be written to the address register of the PHI. This is done
by setting A[1:0] = 00b and performing a write cycle with D[7:0] = indirect register address. To write to an indirect
register, the second step consists of writing the desired data to PHI address A[1:0] = 01b. To read an indirect register,
the second step consists of reading the requested data from address 01b.
Read indirect register
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register address
0
0
Register address
Step 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read register data
0
1
Data from register
Write indirect register
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register address
0
0
Register address
Step 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register data
0
1
Data to register
相關(guān)PDF資料
PDF描述
TVS TVS Applications Matrix - Telecom (49k)
TVUSE (64.69 k)
TVX1A101MAA CAPACITOR 100UF 10V Inhalt pro Packung: 500 Stk.
TVX1A102MCA CAPACITOR 1000UF 10V Inhalt pro Packung: 200 Stk.
TVX1A470MAA CAPACITOR 47UF 10V Inhalt pro Packung: 500 Stk.
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP5145EVM 制造商:Texas Instruments 功能描述:TVP5145EVM - Bulk
TVP5145PFP 功能描述:視頻 IC NTSC/PAL/SECAM/ Comp Dig Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
TVP5146 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL / SECAM 4 X 10 BIT DIGITAL VIDEO DECODER WITH MACROVISION DETECTION YPBPR/RGB INPUTS 5 LINE COMB FILTER AND SCART SUPPORT
TVP5146_12 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL/SECAM 4x10-Bit Digital Video Decoder With Macrovision?￡a Detection, YPbPr/RGB Inputs, 5-Line Comb Filter, and SCART Support
TVP5146EVM 功能描述:視頻 IC 開發(fā)工具 TVP5146 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Boards 類型:YPbPr to RGBHV Converters 工具用于評估:LMH1251 工作電源電壓:5 V
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*