參數(shù)資料
型號： TSPC603R
英文描述： TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz
中文描述： TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫
文件頁數(shù)： 32/44頁
文件大?。?/td> 636K
代理商： TSPC603R
32
TSPC603R
2125A
–
HIREL
–
04/02
Although exceptions have other characteristics as well, such as whether they are maskable or non maskable, the distinc-
tions shown in Table 15 define categories of exceptions that the 603r handles uniquely. Note that Table 15 includes no
synchronous imprecise instructions. While the PowerPC architecture supports imprecise handling of floating-point excep-
tions, the 603r implements these exception modes as precise exceptions.
The 603r
’
s exceptions, and conditions that cause them, are listed in Table 16. Exceptions that are specific to the 603r are
indicated.
Table 16.
Exceptions and Conditions
Exception Type
Vector Offset
(hex)
Causing Conditions
Reserved
00000
—
System Reset
00100
A system reset is caused by the assertion of either SRESET or HRESET.
Machine Check
00200
A machine check is caused by the assertion of the TEA signal during a data bus
transaction, assertion of MCP, or an address or data parity error.
DSI
00300
The cause of a DSI exception can be determined by the bit settings in the DSISR, listed as
follows:
1 Set if the translation of an attempted access is not found in the primary hash table entry
group (HTEG), or in the rehashed secondary HTEG, or in the range of the DBAT register;
otherwise cleared.
4 Set if a memory access is not permitted by the page or DBAT protection mechanism;
otherwise cleared.
5 Set by an eciwx or ecowx instruction if the access is to an address that is marked as
write-through, or execution of a load/store instruction that accesses a direct-store segment.
6 Set for a store operation and cleared for a load operation.
11 Set if eciwx or ecowx is used and EAR[E] is cleared.
ISI
00400
An ISI exception is caused when an instruction fetch cannot be performed for any of the
following reasons:
The effective (logical) address cannot be translated. That is, there is a page fault for this
portion of the translation, so an ISI exception must be taken to load the PTE (and possibly
the page) into memory.
The fetch access violates memory protection. If the key bits (Ks and Kp) in the segment
register and the PP bits in the PTE are set to prohibit read access, instructions cannot be
fetched from this location.
External interrupt
00500
An external interrupt is caused when MSR[EE] = 1 and the INT signal is asserted.
Alignment
00600
An alignment exception is caused when the 603e cannot perform a memory access for any
of the reasons described below:
The operand of a floating-point load or store instruction is not word-aligned.
The operand of lmw, stmw, lwarx, and stwcx, instructions are not aligned.
The operand of a single-register load or store operation is not aligned, and the 603e is in
little-endian mode.
The instruction is lmw, stmw, lswi, lwsx, stswi, stswx and the 603e is in little-endian mode.
The operand of dcbz is in storage that is write-through-required, or caching inhibited.
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