參數(shù)資料
型號(hào): TSPC603R
英文描述: TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz
中文描述: TSPC603R [更新4 / 02。 44頁(yè)] 32位RISC微處理器。 166-300兆赫
文件頁(yè)數(shù): 25/44頁(yè)
文件大?。?/td> 636K
代理商: TSPC603R
25
TSPC603R
2125A
HIREL
04/02
Block address translation (BAT) arrays - The PowerPC architecture defines 16 BAT
registers, divided into four pairs of data BATs (DBATs) and four pairs of instruction
BATs (IBATs). See Figure 13 for a list of the SPR numbers for the BAT arrays.
The following supervisor-level SPRs are implementation-specific to the 603r:
The DMISS and IMISS registers are read-only registers that are loaded
automatically upon an instruction or data TLB miss.
The HASH1 and HASH2 registers contain the physical addresses of the primary
and secondary page table entry groups (PTEGs).
The ICMP and DCMP registers contain a duplicate of the first word in the page table
entry (PTE) for which the table search is looking.
The Required Physical Address (RPA) register is loaded by the processor with the
second word of the correct PTE during a page table search.
The hardware implementation (HID0 and HID1) registers provide the means for
enabling the 603r
s checkstops and features, and allows software to read the
configuration of the PLL configuration signals.
The Instruction Address Breakpoint Register (IABR) is loaded with an instruction
address that is compared to instruction addresses in the dispatch queue. When an
address match occurs, an instruction address breakpoint exception is generated.
Figure 13 shows all the 603r registers available at the user and supervisor level. The
number to the right of the SPRs indicate the number that is used in the syntax of the
instruction operands to access the register.
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