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參數(shù)資料
| 型號： | TSPC603R |
| 英文描述： | TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz |
| 中文描述： | TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫 |
| 文件頁數(shù)： | 13/44頁 |
| 文件大?。?/td> | 636K |
| 代理商： | TSPC603R |
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13
TSPC603R
2125A
–
HIREL
–
04/02
Programmable Power Modes
The 603r provides four programmable power states
—
full power, doze, nap and sleep.
Software selects these modes by setting one (and only one) of the three power saving
mode bits. Hardware can enable a power management state through external asynchro-
nous interrupts The hardware interrupt causes the transfer of program flow to interrupt
handler code. The appropriate mode is then set by the software. The 603r provides a
separate interrupt and interrupt vector for power management
—
the system manage-
ment interrupt (SMI). The 603r also contains a decrement timer which allows it to enter
the nap or doze mode for a predetermined amount of time and then return to full power
operation through the decrementer interrupt (DI). Note that the 603r cannot switch from
on power management mode to another without first returning to full on mode. The nap
and sleep modes disable bus snooping; therefore, a hardware handshake is provided to
ensure coherency before the 603r enters these power management modes. Table 8
summarizes the four power states.
Note:
1. Exceptions are referred to as interrupts in the architecture specification
Power Management Modes
The following sections describe the characteristics of the 603r
’
s power management
modes, the requirements for entering and exiting the various modes, and the system
capabilities provided by the 603r while the power management modes are active.
FULL-Power Mode with DPM Disabled:
Full-power mode with DPM disabled power
mode is selected when the DPM enable bit (bit 11) in HID0 is cleared.
Default state following power-up and HRESET.
All functional units are operating at full processor speed at all times.
FULL-Power Mode with DPM Enabled:
Full-power mode with DPM enabled (HID0[11]
= 1) provides on-chip power management without affecting the functionality or perfor-
mance of the 603r.
Required functional units are operating at full processor speed.
Functional units are clocked only when needed.
No software or hardware intervention required after mode is set.
Software/hardware and performance transparent.
Doze Mode:
Doze mode disables most functional units but maintains cache coherency
by enabling the bus interface unit and snooping. A snoop hit will cause the 603r to
enable the data cache, copy the data back to memory, disable the cache, and fully
return to the doze state.
Most functional units disabled.
Table 8.
Power PC 603r Microprocessor Programmable Power Modes
PM Mode
Functioning Units
Activation Method
Full-power Wake Up Method
Full Power
All units active
—
—
Full Power (with DPM)
Requested logic by demand
By instruction dispatch
—
Doze
- Bus snooping
- Data cache as needed
- Decrementer timer
Controlled by SW
External asynchronous exceptions
(1)
Decrementer interrupt
Reset
Nap
Decrementer timer
Controlled by hardware and
software
External asynchronous exceptions
Decrementer interrupt
Reset
Sleep
None
Controlled by hardware and
software
External asynchronous exceptions
Reset
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